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High-level synthesis
Creation of hardware designs from software code

High-level synthesis (HLS), sometimes referred to as C synthesis, electronic system-level (ESL) synthesis, algorithmic synthesis, or behavioral synthesis, is an automated design process that takes an abstract behavioral specification of a digital system and finds a register-transfer level structure that realizes the given behavior.

Synthesis begins with a high-level specification of the problem, where behavior is generally decoupled from low-level circuit mechanics such as clock-level timing. Early HLS explored a variety of input specification languages, although recent research and commercial applications generally accept synthesizable subsets of ANSI C/C++/SystemC/MATLAB. The code is analyzed, architecturally constrained, and scheduled to transcompile from a transaction-level model (TLM) into a register-transfer level (RTL) design in a hardware description language (HDL), which is in turn commonly synthesized to the gate level by the use of a logic synthesis tool.

The goal of HLS is to let hardware designers efficiently build and verify hardware, by giving them better control over optimization of their design architecture, and through the nature of allowing the designer to describe the design at a higher level of abstraction while the tool does the RTL implementation. Verification of the RTL is an important part of the process.

Hardware can be designed at varying levels of abstraction. The commonly used levels of abstraction are gate level, register-transfer level (RTL), and algorithmic level.

While logic synthesis uses an RTL description of the design, high-level synthesis works at a higher level of abstraction, starting with an algorithmic description in a high-level language such as SystemC and ANSI C/C++. The designer typically develops the module functionality and the interconnect protocol. The high-level synthesis tools handle the micro-architecture and transform untimed or partially timed functional code into fully timed RTL implementations, automatically creating cycle-by-cycle detail for hardware implementation. The (RTL) implementations are then used directly in a conventional logic synthesis flow to create a gate-level implementation.

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History

Early academic work extracted scheduling, allocation, and binding as the basic steps for high-level-synthesis. Scheduling partitions the algorithm in control steps that are used to define the states in the finite-state machine. Each control step contains one small section of the algorithm that can be performed in a single clock cycle in the hardware. Allocation and binding maps the instructions and variables to the hardware components, multiplexers, registers and wires of the data path.

First generation behavioral synthesis was introduced by Synopsys in 1994 as Behavioral Compiler7 and used Verilog or VHDL as input languages. The abstraction level used was partially timed (clocked) processes. Tools based on behavioral Verilog or VHDL were not widely adopted in part because neither languages nor the partially timed abstraction were well suited to modeling behavior at a high level. 10 years later, in early 2004, Synopsys end-of-lifed Behavioral Compiler.8

In 1998, Forte Design Systems introduced its Cynthesizer tool which used SystemC as an entry language instead of Verilog or VHDL. Cynthesizer was adopted by many Japanese companies in 2000 as Japan had a very mature SystemC user community. The first high-level synthesis tapeout was achieved in 2001 by Sony using Cynthesizer. Adoption in the United States started in earnest in 2008.

In 2006, an efficient and scalable "SDC modulo scheduling" technique was developed on control and data flow graphs 9 and was later extended to pipeline scheduling.10 This technique uses the integer linear programming formulation. But it shows that the underlying constraint matrix is totally unimodular (after approximating the resource constraints). Thus, the problem can be solved in polynomial time optimally using a linear programming solver in polynomial time. This work was inducted to the FPGA and Reconfigurable Computing Hall of Fame 2022.11

The SDC scheduling algorithm was implemented in the xPilot HLS system12 developed at UCLA,13 and later licensed to the AutoESL Design Technologies, a spin-off from UCLA. AutoESL was acquired by Xilinx (now part of AMD) in 2011,14 and the HLS tool developed by AutoESL became the base of Xilinx HLS solutions, Vivado HLS and Vitis HLS, widely used for FPGA designs.

Source input

The most common source inputs for high-level synthesis are based on standard languages such as ANSI C/C++, SystemC and MATLAB.

High-level synthesis typically also includes a bit-accurate executable specification as input, since to derive an efficient hardware implementation, additional information is needed on what is an acceptable Mean-Square Error or Bit-Error Rate etc. For example, if the designer starts with an FIR filter written using the "double" floating type, before he can derive an efficient hardware implementation, they need to perform numerical refinement to arrive at a fixed-point implementation. The refinement requires additional information on the level of quantization noise that can be tolerated, the valid input ranges etc. This bit-accurate specification makes the high level synthesis source specification functionally complete.15 Normally the tools infer from the high level code a Finite State Machine and a Datapath that implement arithmetic operations.

Process stages

The high-level synthesis process consists of a number of activities. Various high-level synthesis tools perform these activities in different orders using different algorithms. Some high-level synthesis tools combine some of these activities or perform them iteratively to converge on the desired solution.16

  • Lexical processing
  • Algorithm optimization
  • Control/Dataflow analysis
  • Library processing
  • Resource allocation
  • Scheduling
  • Functional unit binding
  • Register binding
  • Output processing
  • Input Rebundling

Functionality

In general, an algorithm can be performed over many clock cycles with few hardware resources, or over fewer clock cycles using a larger number of ALUs, registers and memories. Correspondingly, from one algorithmic description, a variety of hardware microarchitectures can be generated by an HLS compiler according to the directives given to the tool. This is the same trade off of execution speed for hardware complexity as seen when a given program is run on conventional processors of differing performance, yet all running at roughly the same clock frequency.

Architectural constraints

Synthesis constraints for the architecture can automatically be applied based on the design analysis.17 These constraints can be broken into

  • Hierarchy
  • Interface
  • Memory
  • Loop
  • Low-level timing constraints
  • Iteration

Interface synthesis

Interface Synthesis refers to the ability to accept pure C/C++ description as its input, then use automated interface synthesis technology to control the timing and communications protocol on the design interface. This enables interface analysis and exploration of a full range of hardware interface options such as streaming, single- or dual-port RAM plus various handshaking mechanisms. With interface synthesis the designer does not embed interface protocols in the source description. Examples might be: direct connection, one line, 2 line handshake, FIFO.18

Vendors

Data reported on recent Survey19

StatusCompilerOwnerLicenseInputOutputYearDomainTestbenchFPFixP
In useStratus HLSCadence Design SystemsCommercialC–C++ SystemCRTL2015AllYesYesYes
AUGHTIMA Lab.AcademicC subsetVHDL2012AllYesNoNo
eXCite Archived 2019-09-17 at the Wayback MachineY ExplorationsCommercialCVHDL–Verilog2001AllYesNoYes
BambuPoliMiAcademicCVHDL–Verilog2012AllYesYesNo
BluespecBlueSpec, Inc.BSD-3Bluespec SystemVerilog(Haskell)SystemVerilog2007AllNoNoNo
QCCCacheQ Systems, Inc.CommercialC, C++, FortranHost executable + FPGA bit file (SystemVerilog is intermediate)2018All - multi-core and heterogeneous computeYes (C++)YesYes
CHCAltiumCommercialC subsetVHDL–Verilog2008AllNoYesYes
CoDeveloperImpulse AcceleratedCommercialImpulse-CVHDL2003ImagestreamingYesYesNo
HDL CoderMathWorksCommercialMATLAB, Simulink, Stateflow, SimscapeVHDL, Verilog2003Control systems, signal processing, wireless, radar, communications, image and computer visionYesYesYes
CyberWorkBenchNECCommercialC, BDL, SystemCVHDL–Verilog2004AllCycle,formalYesYes
CatapultSiemens EDACommercialC–C++ SystemCVHDL–Verilog2004AllYesYesYes
DWARVTU. DelftAcademicC subsetVHDL2012AllYesYesYes
GAUTUniversity of Western BrittanyAcademicC, C++VHDL2010DSPYesNoYes
HastlayerLombiq TechnologiesBSD-3C#, C++, F#, ...(.NET)VHDL2015.NETYesYesYes
Instant SoCFPGA CoresCommercialC, C++VHDL–Verilog2019AllYesNoNo
Intel High Level Synthesis CompilerIntel FPGA (Formerly Altera)CommercialC, C++Verilog2017AllYesYesYes
LegUp HLSLegUp ComputingCommercialC, C++Verilog2015AllYesYesYes
LegUp Archived 2020-07-24 at the Wayback MachineUniversity of TorontoAcademicCVerilog2010AllYesYesNo
MaxCompilerMaxelerCommercialMaxJRTL2010Data-flow analysisNoYesNo
ROCCCJacquard Comp.CommercialC subsetVHDL2010StreamingNoYesNo
Symphony CSynopsysCommercialC, C++VHDL–Verilog,SystemC2010AllYesNoYes
VivadoHLS(formerly AutoPilotfrom AutoESL20)XilinxCommercialC–C++ SystemCVHDL–Verilog,SystemC2013AllYesYesYes
KiwiUniversity of CambridgeAcademicC#Verilog2008.NETNoYesYes
CHiMPSUniversity of WashingtonAcademicCVHDL2008AllNoNoNo
gcc2verilogKorea UniversityAcademicCVerilog2011AllNoNoNo
HercuLeSAjax CompilersCommercialC/NACVHDL2012AllYesYesYes
ShangUniversity of Illinois Urbana-ChampaignAcademicCVerilog2013AllYes??
TridentLos Alamos NLAcademicC subsetVHDL2007ScientificNoYesNo
Aban-donedAccelDSPXilinxCommercialMATLABVHDL–Verilog2006DSPYesYesYes
C2HAlteraCommercialCVHDL–Verilog2006AllNoNoNo
CtoVerilogUniversity of HaifaAcademicCVerilog2008AllNoNoNo
DEFACTOUniversity South Cailf.AcademicCRTL1999DSENoNoNo
GarpUniversity of California, BerkeleyAcademicC subsetbitstream2000LoopNoNoNo
MATCHNorthwest UniversityAcademicMATLABVHDL2000ImageNoNoNo
Napa-CSarnoff Corp.AcademicC subsetVHDL–Verilog1998LoopNoNoNo
PipeRenchCarnegie Mellon UniversityAcademicDILbistream2000StreamNoNoNo
SA-CUniversity of ColoradoAcademicSA-CVHDL2003ImageNoNoNo
SeaCucumberBrigham Young UniversityAcademicJavaEDIF2002AllNoYesYes
SPARKUniversity of California, IrvineAcademicCVHDL2003ControlNoNoNo
  • Dynamatic from EPFL/ETH Zurich
  • MATLAB HDL Coder [1] from Mathworks21
  • HLS-QSP from CircuitSutra Technologies22
  • C-to-Silicon from Cadence Design Systems
  • Concurrent Acceleration from Concurrent EDA
  • Symphony C Compiler from Synopsys
  • QuickPlay from PLDA23
  • PowerOpt from ChipVision24
  • Cynthesizer from Forte Design Systems (now Stratus HLS from Cadence Design Systems)
  • Catapult C from Calypto Design Systems, part of Mentor Graphics as of 2015, September 16. In November 2016 Siemens announced plans to acquire Mentor Graphics, Mentor Graphics became styled as "Mentor, a Siemens Business". In January 2021, the legal merger of Mentor Graphics with Siemens was completed - merging into the Siemens Industry Software Inc legal entity. Mentor Graphics' name was changed to Siemens EDA, a division of Siemens Digital Industries Software.25
  • PipelineC [2]
  • CyberWorkBench from NEC26
  • Mega Hardware 27
  • C2R from CebaTech28
  • CoDeveloper from Impulse Accelerated Technologies
  • HercuLeS by Nikolaos Kavvadias29
  • Program In/Code Out (PICO) from Synfora, acquired by Synopsys in June 201030
  • xPilot from University of California, Los Angeles31
  • Vsyn from vsyn.ru32
  • ngDesign from SynFlow33

See also

Further reading

  • Jason Cong, Jason Lau, Gai Liu, Stephen Neuendorffer, Peichen Pan, Kees Vissers, Zhiru Zhang.  FPGA HLS Today: Successes, Challenges, and Opportunities. ACM Transactions on Reconfigurable Technology and Systems, Volume 15, Issue 4, Article No. 5, pp 1–42, December 2022, https://doi.org/10.1145/3530775.
  • Michael Fingeroff (2010). High-Level Synthesis Blue Book. Xlibris[self-published source] Corporation. ISBN 978-1-4500-9724-6.
  • Coussy, P.; Gajski, D. D.; Meredith, M.; Takach, A. (2009). "An Introduction to High-Level Synthesis". IEEE Design & Test of Computers. 26 (4): 8–17. doi:10.1109/MDT.2009.69. S2CID 52870966.
  • Ewout S. J. Martens; Georges Gielen (2008). High-level modeling and synthesis of analog integrated systems. Springer. ISBN 978-1-4020-6801-0.
  • Saraju Mohanty; N. Ranganathan; E. Kougianos & P. Patra (2008). Low-Power High-Level Synthesis for Nanoscale CMOS Circuits. Springer. ISBN 978-0387764733.
  • Alice C. Parker; Yosef Tirat-Gefen; Suhrid A. Wadekar (2007). "System-Level Design". In Wai-Kai Chen (ed.). The VLSI handbook (2nd ed.). CRC Press. ISBN 978-0-8493-4199-1. chapter 76.
  • Shahrzad Mirkhani; Zainalabedin Navabi (2007). "System Level Design Languages". In Wai-Kai Chen (ed.). The VLSI handbook (2nd ed.). CRC Press. ISBN 978-0-8493-4199-1. chapter 86. covers the use of C/C++, SystemC, TML and even UML
  • Liming Xiu (2007). VLSI circuit design methodology demystified: a conceptual taxonomy. Wiley-IEEE. ISBN 978-0-470-12742-1.
  • John P. Elliott (1999). Understanding behavioral synthesis: a practical guide to high-level design. Springer. ISBN 978-0-7923-8542-4.
  • Nane, Razvan; Sima, Vlad-Mihai; Pilato, Christian; Choi, Jongsok; Fort, Blair; Canis, Andrew; Chen, Yu Ting; Hsiao, Hsuan; Brown, Stephen; Ferrandi, Fabrizio; Anderson, Jason; Bertels, Koen (2016). "A Survey and Evaluation of FPGA High-Level Synthesis Tools". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 35 (10): 1591–1604. doi:10.1109/TCAD.2015.2513673. hdl:11311/998432. S2CID 8749577.
  • Gupta, Rajesh; Brewer, Forrest (2008). "High-Level Synthesis: A Retrospective". "High-level Synthesis: A Retrospective". Springer. pp. 13–28. doi:10.1007/978-1-4020-8588-8_2. ISBN 978-1-4020-8587-1.

References

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  5. Bowyer, Bryan (2005-05-02). "The 'why' and 'what' of algorithmic synthesis". EE Times. Retrieved 2016-10-03. https://www.eetimes.com/the-why-and-what-of-algorithmic-synthesis/ ↩

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  9. Cong, Jason; Fan, Yiping; Han, Guoling; Jiang, Wei; Zhang, Zhiru (September 2006). "Platform-Based Behavior-Level and System-Level Synthesis". 2006 IEEE International SOC Conference. IEEE. pp. 199–202. doi:10.1109/socc.2006.283880. ISBN 0-7803-9782-7. 0-7803-9782-7 ↩

  10. Zhang, Zhiru; Liu, Bin (2013). 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) (PDF). IEEE. pp. 211–218. ISBN 978-1-4799-1071-7. 978-1-4799-1071-7 ↩

  11. Cong, Jason; Bin Liu; Neuendorffer, Stephen; Noguera, Juanjo; Vissers, Kees; Zhiru Zhang (April 2011). "High-Level Synthesis for FPGAs: From Prototyping to Deployment". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 30 (4): 473–491. doi:10.1109/tcad.2011.2110592. ISSN 0278-0070. https://dx.doi.org/10.1109/tcad.2011.2110592 ↩

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  14. Cong, Jason; Bin Liu; Neuendorffer, Stephen; Noguera, Juanjo; Vissers, Kees; Zhiru Zhang (April 2011). "High-Level Synthesis for FPGAs: From Prototyping to Deployment". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 30 (4): 473–491. doi:10.1109/tcad.2011.2110592. ISSN 0278-0070. https://dx.doi.org/10.1109/tcad.2011.2110592 ↩

  15. Multiple Word-Length High-Level Synthesis EURASIP Journal on Embedded Systems http://www.hindawi.com/GetArticle.aspx?doi=10.1155/2008/916867&e=html ↩

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  29. "Nikolaos Kavvadias - HercuLeS high-level synthesis tool". Nkavvadias.com. Retrieved 2016-10-03. http://www.nkavvadias.com/hercules/ ↩

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