Menu
Home Explore People Places Arts History Plants & Animals Science Life & Culture Technology
On this page
Transaction-level modeling
Approach for digital systems design

Transaction-level modeling (TLM) is a system-level approach in electronic design automation used primarily for designing and verifying complex systems-on-chip and electronic systems. Unlike detailed register-transfer level (RTL) modeling, TLM focuses on abstracting data transactions between functional blocks, enabling faster simulations with sufficient accuracy for design and software development. Typically implemented with the SystemC language and libraries standardized by the Open SystemC Initiative, TLM models use channel interfaces like FIFOs to represent communication buses. This abstraction eases experimentation with bus architectures and facilitates early system validation through virtual platforms, bridging high-level system requirements and detailed hardware description languages such as VHDL or Verilog.

We don't have any images related to Transaction-level modeling yet.
We don't have any YouTube videos related to Transaction-level modeling yet.
We don't have any PDF documents related to Transaction-level modeling yet.
We don't have any Books related to Transaction-level modeling yet.
We don't have any archived web articles related to Transaction-level modeling yet.

Background and history

Early development (1990s-2000s)

Transaction-level modeling emerged in the late 1990s and early 2000s as a direct response to the increasing complexity of system-on-chip designs and the limitations of traditional register-transfer level (RTL) modeling for system-level verification and software development.11 The semiconductor industry was experiencing a widening disparity between design complexity and designer productivity.12

The foundational concepts of TLM were developed simultaneously by several research groups and companies. Cadence Design Systems introduced early transaction-level concepts in their SpecC language in the mid-1990s,13 while Synopsys developed similar concepts in their SystemC methodology starting in 1999.14 In 2000, Thorsten Grötker, R&D manager at Synopsys was preparing a presentation on the communication mechanism in what was to become the SystemC 2.0 standard, and referred to it as "transaction-based modeling". Gilles Baillieu, then a corporate application engineer at Synopsys, insisted that the new term had to contain "level", as in "register-transfer level" or "behavioral level". The fact that TLM does not denote a single level of abstraction but rather a modeling technique didn't make him change his mind. It had to be "level" in order to make it stick. So it became "TLM".

SystemC and OSCI formation

The development of SystemC proved crucial to TLM's adoption. SystemC was initially developed by Synopsys in 1999 as a C++-based system-level modeling language.15 In 2000, the Open SystemC Initiative (OSCI) was formed as an independent consortium to develop and promote SystemC as an open standard.16 Founding members included Synopsys, Cadence Design Systems, CoWare, and several major semiconductor companies including ARM Holdings, Infineon Technologies, and STMicroelectronics.17 The organization developed the OSCI simulator for open use and distribution.

Since those early days SystemC has been adopted as the language of choice for high level synthesis, connecting the design modeling and virtual prototype application domains with the functional verification and automated path gate level implementation. This offers project teams the ability to produce one model for multiple purposes. At the 2010 DVCon event, OSCI produced a specification of the first synthesizable subset of SystemC for industry standardization.

TLM 1.0 standardization (2005)

The first standardized TLM methodology, known as TLM-1.0, was released by OSCI in 2005.18 TLM-1.0 introduced fundamental concepts including:

  • Basic transaction interfaces for communication
  • FIFO and signal-based communication channels
  • Simple request-response transaction protocols
  • Basic timing annotations

The TLM-1.0 standard was primarily focused on functional modeling and provided limited support for detailed timing analysis.19

TLM 2.0 evolution and IEEE standardization (2008-2011)

TLM-2.0, released in 2008, represented a major advancement in transaction-level modeling methodology.20 The new standard introduced several key innovations:

  • Generic payloads for standardized transaction representation
  • Multiple timing models (untimed, loosely timed, approximately timed)
  • Standardized socket interfaces for interoperability
  • Enhanced debugging and analysis capabilities21

TLM-2.0 was subsequently incorporated into the IEEE 1666-2011 standard for SystemC, providing official recognition and broader industry acceptance.22

Industry adoption and commercial tools

By the mid-2000s, major EDA companies began incorporating TLM support into their commercial tools. Mentor Graphics (now Siemens EDA) introduced TLM support in their ModelSim simulator in 2004,23 followed by Cadence Design Systems with their Incisive platform in 2005.24 Virtual platform companies such as CoWare (acquired by Synopsys in 2010),25 Vast Systems (acquired by Synopsys in 2007), and VaST Systems Technology contributed significantly to TLM's commercial adoption by providing high-performance virtual platforms based on TLM methodology.26

Modern developments (2010s-present)

The 2010s saw TLM become standard practice in the semiconductor industry, particularly for ARM-based SoC design. ARM Holdings released comprehensive TLM models of their processor architectures, including ARM Cortex-A and ARM Cortex-M series processors.27 The rise of artificial intelligence and machine learning accelerators in the late 2010s created new demands for TLM modeling, leading to specialized libraries and methodologies for modeling neural processing units and other AI hardware.28 In 2020, OSCI merged with Accellera, consolidating SystemC and TLM development under a single organization and ensuring continued evolution of the standards.29

Key Concepts

See also

References

  1. The VLSI handbook. Wai-Kai Chen (2 ed.). Boca Raton, FL: CRC/Taylor & Francis. 2007. ISBN 978-0-8493-4199-1. OCLC 70699056.{{cite book}}: CS1 maint: others (link) 978-0-8493-4199-1 ↩

  2. The VLSI handbook. Wai-Kai Chen (2 ed.). Boca Raton, FL: CRC/Taylor & Francis. 2007. ISBN 978-0-8493-4199-1. OCLC 70699056.{{cite book}}: CS1 maint: others (link) 978-0-8493-4199-1 ↩

  3. The VLSI handbook. Wai-Kai Chen (2 ed.). Boca Raton, FL: CRC/Taylor & Francis. 2007. ISBN 978-0-8493-4199-1. OCLC 70699056.{{cite book}}: CS1 maint: others (link) 978-0-8493-4199-1 ↩

  4. "IEEE Standard for Standard SystemC Language Reference Manual". IEEE Std 1666-2011. 2012. doi:10.1109/IEEESTD.2012.6134619. /wiki/Doi_(identifier) ↩

  5. Ghenassia, Frank, ed. (2005). Transaction-Level Modeling with SystemC. Springer. ISBN 978-0-387-26233-4. {{cite book}}: Check |isbn= value: checksum (help) 978-0-387-26233-4 ↩

  6. T. Grötker, S. Liao, G. Martin, S. Swan, System Design with SystemC. Springer, 2002, Chapter 8., pp. 131. ISBN 1-4020-7072-1 (quoted with permission) /wiki/ISBN_(identifier) ↩

  7. "SystemC Standards". Accellera Systems Initiative. Retrieved 2024-01-15. https://www.accellera.org/downloads/standards/systemc ↩

  8. L. Cai, D. Gajski, Transaction Level Modeling: An Overview, in proceedings of the Int. Conference on HW/SW Codesign and System Synthesis (CODES-ISSS), Oct. 2003, pp. 19–24 ↩

  9. Schirner, Gunar (2013). Virtual Platforms in System-Level Design. Design Automation Conference. pp. 804–809. doi:10.1145/2463209.2488885. /wiki/Doi_(identifier) ↩

  10. The VLSI handbook. Wai-Kai Chen (2 ed.). Boca Raton, FL: CRC/Taylor & Francis. 2007. ISBN 978-0-8493-4199-1. OCLC 70699056.{{cite book}}: CS1 maint: others (link) 978-0-8493-4199-1 ↩

  11. Gajski, Daniel D. (2000). SpecC: Specification Language and Methodology. Kluwer Academic Publishers. ISBN 978-0-7923-7822-5. {{cite book}}: Check |isbn= value: checksum (help) 978-0-7923-7822-5 ↩

  12. International Technology Roadmap for Semiconductors: Design (Report). Semiconductor Industry Association. 1999. http://www.itrs.net/ ↩

  13. Gajski, Daniel D. (1997). SpecC: A Design Language for System Level Design. Design Automation Conference. pp. 464–469. doi:10.1145/266021.266138. /wiki/Doi_(identifier) ↩

  14. Grötker, Thorsten (2003). "SystemC: Past, Present, and Future". IEEE Design & Test. 20 (6): 72–77. doi:10.1109/MDT.2003.1246169. /wiki/Doi_(identifier) ↩

  15. "Synopsys Introduces SystemC for System-Level Design". EE Times. 1999-10-04. https://www.eetimes.com/synopsys-introduces-systemc/ ↩

  16. "Open SystemC Initiative Formed to Advance System-Level Design" (Press release). Open SystemC Initiative. 2000-09-12. ↩

  17. "Accellera History". Accellera Systems Initiative. Retrieved 2024-01-15. https://www.accellera.org/about/history ↩

  18. "OSCI Releases Transaction Level Modeling Standard" (Press release). Open SystemC Initiative. 2005-06-15. ↩

  19. Ghenassia, Frank, ed. (2005). "TLM-1.0 Standard". Transaction-Level Modeling with SystemC: TLM Concepts and Applications for Embedded Systems. Springer. pp. 87–124. ISBN 978-0-387-26233-4. {{cite book}}: Check |isbn= value: checksum (help) 978-0-387-26233-4 ↩

  20. "OSCI Releases TLM-2.0 Standard for Transaction-Level Modeling" (Press release). Open SystemC Initiative. 2008-06-10. ↩

  21. Aynsley, John (2009). "TLM-2.0 Reference". ASIC and FPGA Verification: A Guide to Component Modeling. Springer. pp. 145–198. ISBN 978-1-4419-0564-5. {{cite book}}: Check |isbn= value: checksum (help) 978-1-4419-0564-5 ↩

  22. IEEE Standard for Standard SystemC Language Reference Manual (Technical report). IEEE. 2012. doi:10.1109/IEEESTD.2012.6134619. {{cite tech report}}: Unknown parameter |standard= ignored (help) /wiki/Doi_(identifier) ↩

  23. "Mentor Graphics Adds SystemC TLM to ModelSim". EE Times. 2004-03-15. ↩

  24. "Cadence Introduces Transaction-Level Modeling Flow" (Press release). Cadence Design Systems. 2005-09-12. ↩

  25. "Synopsys Acquires CoWare for Virtual Prototyping". EE Times. 2010-02-22. ↩

  26. Virtual Prototyping Market Analysis (Report). Gary Smith EDA. 2010. ↩

  27. ARM Fast Models: System-Level Modeling for Software Development, ARM Holdings, 2012 ↩

  28. Chen, Li (2019). Transaction-Level Modeling for AI Accelerator Design. Design Automation Conference. pp. 1–6. doi:10.1145/3316781.3317788. /wiki/Doi_(identifier) ↩

  29. "Accellera and OSCI Merge to Advance System-Level Design Standards" (Press release). Accellera Systems Initiative. 2020-01-15. ↩