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Zen (first generation)
2017 AMD 14-nanometre processor microarchitecture

Zen is the first iteration in the Zen family of computer processor microarchitectures from AMD. It was first used with their Ryzen series of CPUs in February 2017. The first Zen-based preview system was demonstrated at E3 2016, and first substantially detailed at an event hosted a block away from the Intel Developer Forum 2016. The first Zen-based CPUs, codenamed "Summit Ridge", reached the market in early March 2017, Zen-derived Epyc server processors launched in June 2017 and Zen-based APUs arrived in November 2017.

Zen is a clean sheet design that differs from AMD's previous long-standing Bulldozer architecture. Zen-based processors use a 14 nm FinFET process, are reportedly more energy efficient, and can execute significantly more instructions per cycle. SMT has been introduced, allowing each core to run two threads. The cache system has also been redesigned, making the L1 cache write-back. Zen processors use three different sockets: desktop Ryzen chips use the AM4 socket, bringing DDR4 support; the high-end desktop Zen-based Threadripper chips support quad-channel DDR4 memory and offer 64 PCIe 3.0 lanes (vs 24 lanes), using the TR4 socket; and Epyc server processors offer 128 PCIe 3.0 lanes and octa-channel DDR4 using the SP3 socket.

Zen is based on a SoC design. The memory controller and the PCIe, SATA, and USB controllers are incorporated into the same chip(s) as the processor cores. This has advantages in bandwidth and power, at the expense of chip complexity and die area. This SoC design allows the Zen microarchitecture to scale from laptops and small-form factor mini PCs to high-end desktops and servers.

By 2020, 260 million Zen cores have already been shipped by AMD.

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Design

According to AMD, the main focus of Zen is on increasing per-core performance.91011

New or improved features include:12

  • The L1 cache has been changed from write-through to write-back, allowing for lower latency and higher bandwidth.
  • SMT (simultaneous multithreading) architecture allows for two threads per core, a departure from the CMT (clustered multi-thread) design used in the previous Bulldozer architecture. This is a feature previously offered in some IBM, Intel and Oracle processors.13
  • A fundamental building block for all Zen-based CPUs is the Core Complex (CCX) consisting of four cores and their associated caches. Processors with more than four cores consist of multiple CCXs connected by Infinity Fabric.14 Processors with non-multiple-of-four core counts have some cores disabled.
  • Four ALUs, two AGUs/load–store units, and two floating-point units per core.15
  • Newly introduced "large" micro-operation cache.16
  • Each SMT core can dispatch up to six micro-ops per cycle (a combination of 6 integer micro-ops and 4 floating point micro-ops per cycle).1718
  • Close to 2× faster L1 and L2 bandwidth, with total L3 cache bandwidth up 5×.
  • Clock gating.
  • Larger retire, load, and store queues.
  • Improved branch prediction using a hashed perceptron system with Indirect Target Array similar to the Bobcat microarchitecture,19 something that has been compared to a neural network by AMD engineer Mike Clark.20
  • The branch predictor is decoupled from the fetch stage.
  • A dedicated stack engine for modifying the stack pointer, similar to that of Intel Haswell and Broadwell processors.21
  • Move elimination, a method that reduces physical data movement to reduce power consumption.
  • Binary compatibility with Intel's Skylake (excluding VT-x and private MSRs):
    • RDSEED support, a set of high-performance hardware random number generator instructions introduced in Broadwell.22
    • Support for the SMAP, SMEP, XSAVEC/XSAVES/XRSTORS, and CLFLUSHOPT instructions.23
    • ADX support.
    • SHA support.
  • CLZERO instruction for clearing a cache line.24 Useful for handling ECC-related Machine-check exceptions.
  • PTE (page table entry) coalescing, which combines 4 kB page tables into 32 kB page size.
  • "Pure Power" (more accurate power monitoring sensors).25
    • Support for intel-style running average power limit (RAPL) measurement.26
  • Smart Prefetch.
  • Precision Boost.
  • eXtended Frequency Range (XFR), an automated overclocking feature which boosts clock speeds beyond the advertised turbo frequency.27

This is the first time in a very long time that we engineers have been given the total freedom to build a processor from scratch and do the best we can do. It is a multi-year project with a really large team. It's like a marathon effort with some sprints in the middle. The team is working very hard, but they can see the finish line. I guarantee that it will deliver a huge improvement in performance and power consumption over the previous generation.

— Suzanne Plummer, Zen team leader, on September 19th, 2015.28

The Zen architecture is built on a 14 nanometer FinFET process subcontracted to GlobalFoundries,29 which in turn licenses its 14 nm process from Samsung Electronics.30 This gives greater efficiency than the 32 nm and 28 nm processes of previous AMD FX CPUs and AMD APUs, respectively.31 The "Summit Ridge" Zen family of CPUs use the AM4 socket and feature DDR4 support and a 95 W TDP (thermal design power).32 While newer roadmaps don't confirm the TDP for desktop products, they suggest a range for low-power mobile products with up to two Zen cores from 5 to 15 W and 15 to 35 W for performance-oriented mobile products with up to four Zen cores.33

Each Zen core can decode four instructions per clock cycle and includes a micro-op cache which feeds two schedulers, one each for the integer and floating point segments.3435 Each core has two address generation units, four integer units, and four floating point units. Two of the floating point units are adders, and two are multiply-adders. However, using multiply-add-operations may prevent simultaneous add operation in one of the adder units.36 There are also improvements in the branch predictor. The L1 cache size is 64 KB for instructions per core and 32 KB for data per core. The L2 cache size 512 KB per core, and the L3 is 1–2 MB per core. L3 caches offer 5× the bandwidth of previous AMD designs.

History and development

AMD began planning the Zen microarchitecture shortly after re-hiring Jim Keller in August 2012.37 AMD formally revealed Zen in 2015.

The team in charge of Zen was led by Keller (who left in September 2015 after a 3-year tenure) and Zen Team Leader Suzanne Plummer.3839 The Chief Architect of Zen was AMD Senior Fellow Michael Clark.404142

Zen was originally planned for 2017 following the ARM64-based K12 sister core, but on AMD's 2015 Financial Analyst Day it was revealed that K12 was delayed in favor of the Zen design, to allow it to enter the market within the 2016 timeframe,43 with the release of the first Zen-based processors expected for October 2016.44

In November 2015, a source inside AMD reported that Zen microprocessors had been tested and "met all expectations" with "no significant bottlenecks found".4546

In December 2015, it was rumored that Samsung may have been contracted as a fabricator for AMD's 14 nm FinFET processors, including both Zen and AMD's then-upcoming Polaris GPU architecture.47 This was clarified by AMD's July 2016 announcement that products had been successfully produced on Samsung's 14 nm FinFET process.48 AMD stated Samsung would be used "if needed", arguing this would reduce risk for AMD by decreasing dependence on any one foundry.

In December 2019, AMD started putting out first generation Ryzen products built using the second generation Zen+ architecture.49

Advantages over predecessors

Manufacturing process

Processors based on Zen use 14 nm FinFET silicon.50 These processors are reportedly produced at GlobalFoundries.51 Prior to Zen, AMD's smallest process size was 28 nm, as utilized by their Steamroller and Excavator microarchitectures.5253 The immediate competition, Intel's Skylake and Kaby Lake microarchitecture, are also fabricated on 14 nm FinFET;54 though Intel planned to begin the release of 10 nm parts later in 2017.55 Intel was unable to reach this goal, and in 2021, only mobile chips have been produced with the 10nm process. In comparison to Intel's 14 nm FinFET, AMD claimed in February 2017 the Zen cores would be 10% smaller.56 Intel has later announced in July 2018 that 10nm mainstream processors should not be expected before the second half of 2019.57

For identical designs, these die shrinks would use less current (and power) at the same frequency (or voltage). As CPUs are usually power limited (typically up to ~125 W, or ~45 W for mobile), smaller transistors allow for either lower power at the same frequency, or higher frequency at the same power.58

Performance

One of Zen's major goals in 2016 was to focus on performance per-core, and it was targeting a 40% improvement in instructions per cycle (IPC) over its predecessor.59 Excavator, in comparison, offered 4–15% improvement over previous architectures.6061 AMD announced the final Zen microarchitecture actually achieved 52% improvement in IPC over Excavator.62 The inclusion of SMT also allows each core to process up to two threads, increasing processing throughput by better use of available resources.

The Zen processors also employ sensors across the chip to dynamically scale frequency and voltage.63 This allows for the maximum frequency to be dynamically and automatically defined by the processor itself based upon available cooling.

AMD has demonstrated an 8-core/16-thread Zen processor outperforming an equally-clocked Intel Broadwell-E processor in Blender rendering6465 and HandBrake benchmarks.66

Zen supports AVX2 but it requires two clock cycles to complete each AVX2 instruction compared to Intel's one.6768 This difference was corrected in Zen 2.

Memory

Zen supports DDR4 memory (up to eight channels)69 and ECC.70

Pre-release reports stated APUs using the Zen architecture would also support High Bandwidth Memory (HBM).71 However, the first demonstrated APU did not use HBM.72 Previous APUs from AMD relied on shared memory for both the GPU and the CPU.

Power consumption and heat output

Processors built at the 14 nm node on FinFET silicon should show reduced power consumption and therefore heat over their 28 nm and 32 nm non-FinFET predecessors (for equivalent designs), or be more computationally powerful at equivalent heat output/power consumption.

Zen also uses clock gating,73 reducing the frequency of underutilized portions of the core to save power. This comes from AMD's SenseMI technology, using sensors across the chip to dynamically scale frequency and voltage.74

Enhanced security and virtualization support

Zen added support for AMD's Secure Memory Encryption (SME) and AMD's Secure Encrypted Virtualization (SEV). Secure Memory Encryption is real-time memory encryption done per page table entry. Encryption occurs on a hardware AES engine and keys are managed by the onboard "Security" Processor (ARM Cortex-A5) at boot time to encrypt each page, allowing any DDR4 memory (including non-volatile varieties) to be encrypted. AMD SME also makes the contents of the memory more resistant to memory snooping and cold boot attacks.7576

SME can be used to mark individual pages of memory as encrypted through the page tables. A page of memory that is marked encrypted will be automatically decrypted when read from DRAM and will be automatically encrypted when written to DRAM. The SME feature is identified through a CPUID function and enabled through the SYSCFG MSR. Once enabled, page table entries will determine how the memory is accessed. If a page table entry has the memory encryption mask set, then that memory will be accessed as encrypted memory. The memory encryption mask (as well as other related information) is determined from settings returned through the same CPUID function that identifies the presence of the feature.77

The Secure Encrypted Virtualization (SEV) feature allows the memory contents of a virtual machine (VM) to be transparently encrypted with a key unique to the guest VM. The memory controller contains a high-performance encryption engine which can be programmed with multiple keys for use by different VMs in the system. The programming and management of these keys is handled by the AMD Secure Processor firmware which exposes an API for these tasks.78

Connectivity

Incorporating much of the southbridge into the SoC, the Zen CPU includes SATA, USB, and PCI Express NVMe links.7980 This can be augmented by available Socket AM4 chipsets which add connectivity options including additional SATA and USB connections, and support for AMD's Crossfire and Nvidia's SLI.81

AMD, in announcing its Radeon Instinct line, argued that the upcoming Zen-based Naples server CPU would be particularly suited for building deep learning systems.8283 The 12884 PCIe lanes per Naples CPU allows for eight Instinct cards to connect at PCIe x16 to a single CPU. This compares favorably to the Intel Xeon line, with only 40 PCIe lanes.

Features

CPUs

APUs

APU features table

Products

The Zen architecture is used in the current-generation desktop Ryzen CPUs. It is also in Epyc server processors (successor of Opteron processors), and APUs.85[unreliable source]8687

The first desktop processors without graphics processing units (codenamed "Summit Ridge") were initially expected to start selling at the end of 2016, according to an AMD roadmap; with the first mobile and desktop processors of the AMD Accelerated Processing Unit type (codenamed "Raven Ridge") following in late 2017.88 AMD officially delayed Zen until Q1 of 2017. In August 2016, an early demonstration of the architecture showed an 8-core/16-thread engineering sample CPU at 3.0 GHz.89

In December 2016, AMD officially announced the desktop CPU line under the Ryzen brand for release in Q1 2017. It also confirmed Server processors would be released in Q2 2017, and mobile APUs in H2 2017.90

On March 2, 2017, AMD officially launched the first Zen architecture-based octacore Ryzen desktop CPUs. The final clock speeds and TDPs for the 3 CPUs released in Q1 of 2017 demonstrated significant performance-per-watt benefits over the previous K15h (Piledriver) architecture.9192 The octacore Ryzen desktop CPUs demonstrated performance-per-watt comparable to Intel's Broadwell octacore CPUs.9394

In March 2017, AMD also demonstrated an engineering sample of a server CPU based on the Zen architecture. The CPU (codenamed "Naples") was configured as a dual-socket server platform with each CPU having 32 cores/64 threads.9596

Desktop processors

Main article: Ryzen

Common features of Ryzen 1000 desktop CPUs:

  • Socket: AM4.
  • All the CPUs support DDR4-2666 in dual-channel mode.
  • All the CPUs support 24 PCIe 3.0 lanes. 4 of the lanes are reserved as link to the chipset.
  • No integrated graphics.
  • L1 cache: 96 KB (32 KB data + 64 KB instruction) per core.
  • L2 cache: 512 KB per core.
  • Node/fabrication process: GlobalFoundries 14 LP.
Branding and ModelCores(threads)Clock rate (GHz)L3 cache(total)TDPCoreconfig97ReleasedateLaunchprice98
BasePBO1–2(≥3)XFR991–2
Ryzen 71800X1008 (16)3.64.0 (3.7)4.116 MB95 W2 × 4March 2, 2017US $499
PRO 1700X3.43.8 (3.5)3.9June 29, 2017OEM
1700X101March 2, 2017US $399
PRO 17003.03.7 (3.2)3.7565 WJune 29, 2017OEM
1700102March 2, 2017US $329
Ryzen 51600X1036 (12)3.64.0 (3.7)4.195 W2 × 3April 11, 2017US $249
PRO 16003.23.6 (3.4)3.765 WJune 29, 2017OEM
1600104April 11, 2017US $219
1500X1054 (8)3.53.7 (3.6)3.92 × 2US $189
PRO 1500June 29, 2017OEM
14001063.23.4 (3.4)3.458 MBApril 11, 2017US $169
Ryzen 31300X1074 (4)3.53.7 (3.5)3.9July 27, 2017US $129
PRO 1300June 29, 2017OEM
PRO 12003.13.4 (3.1)3.45
1200108July 27, 2017US $109
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Common features of Ryzen 1000 HEDT CPUs:

  • Socket: TR4.
  • All the CPUs support DDR4-2666 in quad-channel mode.
  • All the CPUs support 64 PCIe 3.0 lanes. 4 of the lanes are reserved as link to the chipset.
  • No integrated graphics.
  • L1 cache: 96 KB (32 KB data + 64 KB instruction) per core.
  • L2 cache: 512 KB per core.
  • Node/fabrication process: GlobalFoundries 14LP.
Branding and ModelCores(threads)Clock rate (GHz)L3 cache(total)TDPChipletsCoreconfig109ReleasedateLaunchprice110
BasePBO1–4(≥5)XFR1111–2
RyzenThreadripper1950X11216 (32)3.44.0(3.7)4.232 MB180 W2 × CCD1134 × 4August 10, 2017US $999
1920X11412 (24)3.54 × 3US $799
1900X1158 (16)3.84.0(3.9)16 MB2 × 4August 31, 2017US $549
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Desktop APUs

Ryzen APUs are identified by either the G or GE suffix in their name.

ModelRelease date& priceFabThermal SolutionCPUGPUSocketPCIe lanesDDR4memorysupportTDP(W)
Cores(threads)Clock rate (GHz)CacheModelConfig116Clock(GHz)Processingpower(GFLOPS)117
BaseBoostL1L2L3
Athlon 200GE118September 6, 2018US $55GloFo14LPAMD 65W thermal solution2 (4)3.2—64 KB inst.32 KB dataper core512 KBper core4 MBVega 3192:12:43 CU1.0384AM416 (8+4+4)2667dual-channel35
Athlon Pro 200GE119September 6, 2018OEMOEM
Athlon 220GE120December 21, 2018US $65AMD 65W thermal solution3.4
Athlon 240GE121December 21, 2018US $753.5
Athlon 3000G122November 19, 2019US $491.1424.4
Athlon 300GE123July 7, 2019OEMOEM3.4
Athlon Silver 3050GE124July 21, 2020OEM
Ryzen 3 Pro 2100GE125c. 2019

OEM

3.2??2933dual-channel
Ryzen 3 2200GE126April 19, 2018OEM4 (4)3.23.6Vega 8512:32:168 CU1126
Ryzen 3 Pro 2200GE127May 10, 2018OEM
Ryzen 3 2200GFebruary 12, 2018US $99Wraith Stealth3.53.745–65
Ryzen 3 Pro 2200G128May 10, 2018OEMOEM
Ryzen 5 2400GE129April 19, 2018OEM4 (8)3.23.8RX Vega 11704:44:1611 CU1.25176035
Ryzen 5 Pro 2400GE130May 10, 2018OEM
Ryzen 5 2400G131February 12, 2018132133US $169Wraith Stealth3.63.945–65
Ryzen 5 Pro 2400G134May 10, 2018OEMOEM
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Mobile APUs

ModelReleasedateFabCPUGPUSocketPCIelanesMemorysupportTDP
Cores(threads)Clock rate (GHz)CacheModelConfig135Clock(MHz)Processingpower(GFLOPS)136
BaseBoostL1L2L3
Athlon Pro 200U2019GloFo14LP2 (4)2.33.264 KB inst.32 KB dataper core512 KBper core4 MBRadeon Vega 3192:12:43 CU1000384FP512 (8+4)DDR4-2400dual-channel12–25 W
Athlon 300UJan 6, 20192.43.3
Ryzen 3 2200UJan 8, 20182.53.41100422.4
Ryzen 3 3200UJan 6, 20192.63.51200460.8
Ryzen 3 2300UJan 8, 20184 (4)2.03.4Radeon Vega 6384:24:86 CU1100844.8
Ryzen 3 Pro 2300UMay 15, 2018
Ryzen 5 2500UOct 26, 20174 (8)3.6Radeon Vega 8512:32:168 CU1126.4
Ryzen 5 Pro 2500UMay 15, 2018
Ryzen 5 2600HSep 10, 20183.2DDR4-3200dual-channel35–54 W
Ryzen 7 2700UOct 26, 20172.23.8Radeon RX Vega 10640:40:1610 CU13001664DDR4-2400dual-channel12–25 W
Ryzen 7 Pro 2700UMay 15, 2018Radeon Vega 10
Ryzen 7 2800HSep 10, 20183.3Radeon RX Vega 11704:44:1611 CU1830.4DDR4-3200dual-channel35–54 W
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Ultra-mobile APUs

Dalí

ModelReleasedateFabCPUGPUSocketPCIelanesMemorysupportTDPPart number
Cores(threads)Clock rate (GHz)CacheModelConfig137Clock(GHz)Processingpower(GFLOPS)138
BaseBoostL1L2L3
AMD 3020eJan 6, 202014 nm2 (2)1.22.664 KB inst.32 KB dataper core512 KBper core4 MBRadeonGraphics(Vega)192:12:43 CU1.0384FP512 (8+4)DDR4-2400dual-channel6 WYM3020C7T2OFG
Athlon PRO 3045BQ1 20212.33.2128:8:42 CU1.1281.615 WYM3045C4T2OFG
Athlon Silver 3050UJan 6, 2020YM3050C4T2OFG
Athlon Silver 3050CSep 22, 2020YM305CC4T2OFG
Athlon Silver 3050eJan 6, 20202 (4)1.42.8192:12:43 CU1391.03846 WYM3050C7T2OFG
Athlon PRO 3145BQ1 20212.43.315 WYM3145C4T2OFG
Athlon Gold 3150UJan 6, 2020YM3150C4T2OFG
Athlon Gold 3150CSep 22, 2020YM315CC4T2OFG
Ryzen 3 3250UJan 6, 20202.63.51.2460.8YM3250C4T2OFG
Ryzen 3 3250CSep 22, 2020YM325CC4T2OFG
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Pollock

ModelReleasedateFabCPUGPUSocketPCIelanesMemorysupportTDPPart number
Cores(threads)Clock rate (GHz)CacheModelConfig140Clock(GHz)Processingpower(GFLOPS)141
BaseBoostL1L2L3
AMD 3015eJul 6, 202014 nm2 (4)1.22.364 KB inst.32 KB dataper core512 KBper core4 MBRadeonGraphics(Vega)192:12:43 CU0.6230.4FT512 (8+4)DDR4-1600single-channel6 WAM3015BRP2OFJ
AMD 3015CeApr 29, 2021AM301CBRP2OFJ
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Embedded processors

V1000

In February 2018, AMD announced the V1000 series of embedded Zen+Vega APUs with four SKUs.142 (And three more SKUs in December that year.)

ModelReleasedateFabCPUGPUMemorysupportTDPJunctiontemp.range(°C)
Cores(threads)Clock rate (GHz)CacheModelConfig143Clock(GHz)Processingpower(GFLOPS)144
BaseBoostL1L2L3
V1202BFebruary 2018GloFo14LP2 (4)2.33.264 KB inst.32 KB dataper core512 KBper core4 MBVega 3192:12:163 CU1.0384DDR4-2400dual-channel12–25 W0–105
V1404IDecember 20184 (8)2.03.6Vega 8512:32:168 CU1.11126.4-40–105
V1500B2.2——0–105
V1605BFebruary 20182.03.6Vega 8512:32:168 CU1.11126.4
V1756B3.25DDR4-3200dual-channel35–54 W
V1780BDecember 20183.35—
V1807BFebruary 20183.8Vega 11704:44:1611 CU1.31830.4
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R1000

In 2019, AMD announced the R1000 series of embedded Zen+Vega APUs.

ModelReleasedateFabCPUGPUMemorysupportTDP
Cores(threads)Clock rate (GHz)CacheModelConfig145Clock(GHz)Processingpower(GFLOPS)146
BaseBoostL1L2L3
R1102GFebruary 25, 2020GloFo14LP2 (2)1.22.664 KB inst.32 KB dataper core512 KBper core4 MBVega 3192:12:43 CU1.0384DDR4-2400single-channel6 W
R1305G2 (4)1.52.8DDR4-2400dual-channel8-10 W
R1505GApril 16, 20192.43.312–25 W
R1606G2.63.51.2460.8
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Server processors

Main article: Epyc

AMD announced in March 2017 that it would release a server platform based on Zen, codenamed Naples, in the second quarter of the year. The platform include 1- and 2-socket systems. The CPUs in multi-processor configurations communicate via AMD's Infinity Fabric.147 Each chip supports eight channels of memory and 128 PCIe 3.0 lanes, of which 64 lanes are used for CPU-to-CPU communication through Infinity Fabric when installed in a dual-processor configuration.148 AMD officially revealed Naples under the brand name Epyc in May 2017.149

On June 20, 2017, AMD officially released the Epyc 7000 series CPUs at a launch event in Austin, Texas.150 Common features:

  • SP3 socket
  • Zen microarchitecture
  • GloFo 14 nm process
  • MCM with four System-on-a-chip (SOC) dies, two core complexes (CCX) per SOC die151
  • Eight-channel DDR4-2666 (the 7251 model is limited to DDR4-2400)
  • 128 PCIe 3.0 lanes per socket, 64 of which are used for Infinity Fabric inter-processor links in 2P platforms
  • 7001P series models are limited to uniprocessor operation (1P)
ModelCores(threads)ChipletsCoreconfig152Clock rateCache sizeSocketScalingTDPReleasedateReleasepriceEmbeddedoptions153
Base(GHz)Boost(GHz)L2per coreL3per CCXTotal
7251154155  8 (16)4156  8 × 12.12.9512 KB4 MB36 MB  SP32P120 WJun 2017157  $4757251
72611581592.52.98 MB68 MB2P155/170 WJun 2018160  $5707261
728116116216 (32)  8 × 22.12.74 MB40 MB2P155/170 WJun 2017163  $6507281
73011641652.22.78 MB72 MB2P  $8007301
7351(P)1661672.42.92P (1P)$1100 ($750)7351(735P)
73711681693.13.82P200 WNov 2018170$15507371
7401(P)17117224 (48)  8 × 32.03.08 MB76 MB2P (1P)155/170 WJun 2017173$1850 ($1075)7401(740P)
74511741752.33.22P180 W$24007451
750117617732 (64)  8 × 42.03.08 MB80 MB2P155/170 WJun 2017178$34007501
7551(P)1791802.03.02P (1P)180 W$3400 ($2100)7551(755P)
75711811822.23.02P200 WNov 2018OEM/AWS--
76011831842.23.22P180 WJun 2017185$42007601
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Embedded server processors

In February 2018, AMD also announced the EPYC 3000 series of embedded Zen CPUs.186Common features of EPYC Embedded 3000 series CPUs:

  • Socket: SP4 (31xx and 32xx models use SP4r2 package).
  • All the CPUs support ECC DDR4-2666 in dual-channel mode (3201 supports only DDR4-2133), while 33xx and 34xx models support quad-channel mode.
  • L1 cache: 96 KB (32 KB data + 64 KB instruction) per core.
  • L2 cache: 512 KB per core.
  • All the CPUs support 32 PCIe 3.0 lanes per CCD (max 64 lanes).
  • Fabrication process: GlobalFoundries 14 nm.
ModelCores(threads)Clock rate (GHz)L3 cache(total)TDPChipletsCoreconfig187Releasedate
BaseBoost
All-coreMax
31011884 (4)2.12.92.98 MB35 W1 × CCD1 × 4Feb 2018
31511894 (8)2.716 MB45 W2 × 2
32011908 (8)1.53.13.130 W2 × 4
32511918 (16)2.555 W
325519225–55 WDec 2018
330119312 (12)2.02.153.032 MB65 W2 × CCD4 × 3Feb 2018
335119412 (24)1.92.7560–80 W
340119516 (16)1.852.2585 W4 × 4
345119616 (32)2.152.4580–100 W
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See also

Wikimedia Commons has media related to Zen microarchitecture.

References

  1. Anthony, Sebastian (18 August 2016). "AMD says Zen CPU will outperform Intel Broadwell-E, delays release to 2017". Ars Technica. Archived from the original on 18 August 2016. Retrieved 18 August 2016. https://arstechnica.com/gadgets/2016/08/amd-zen-performance-details-release-date/ ↩

  2. Cutress, Ian. "AMD's Future in Servers: New 7000-Series CPUs Launched and Epyc Analysis". AnandTech. Archived from the original on 21 June 2017. Retrieved 8 August 2017. http://www.anandtech.com/show/11551/amds-future-in-servers-new-7000-series-cpus-launched-and-epyc-analysis ↩

  3. "HP ENVY x360 Convertible Laptop - 15z touch - HP® Official Store". store.hp.com. Archived from the original on 2017-12-10. Retrieved 2017-12-09. http://store.hp.com/us/en/pdp/hp-envy-x360-convertible-laptop-15z-touch-1za07av-1 ↩

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