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Reference.org
Phase-locked loop
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<p>A phase-locked loop or phase lock loop (PLL) is a <a href="/facts/Control_system/8CEjIDlS">control system</a> that generates an output <a href="/facts/Signal_(electrical_engineering)/41YqUJ8c">signal</a> whose <a href="/facts/Phase_(waves)/cpGtuVll">phase</a> is fixed relative to the phase of an input signal. Keeping the input and output phase in lockstep also implies keeping the input and output frequencies the same, thus a phase-locked loop can also track an input frequency. Furthermore, by incorporating a <a href="/facts/Frequency_divider/hf2DDqrp">frequency divider</a>, a PLL can generate a stable frequency that is a multiple of the input frequency. </p><p>These properties are used for clock synchronization, <a href="/facts/Demodulation/GFLGoxFl">demodulation</a>, <a href="/facts/Frequency_synthesis/bsPnGKdr">frequency synthesis</a>, <a href="/facts/Clock_multiplier/p1GVNh7K">clock multipliers</a>, and signal recovery from a noisy communication channel. Since 1969, a single <a href="/facts/Integrated_circuit/fjn6vg7C">integrated circuit</a> can provide a complete PLL building block, and nowadays have output frequencies from a fraction of a <a href="/facts/Hertz/6Wshj5qm">hertz</a> up to many <a href="/facts/Gigahertz/6Wshj5qm">gigahertz</a>. Thus, PLLs are widely employed in <a href="/facts/Radio/XFr909M2">radio</a>, <a href="/facts/Telecommunications/vxoj1cxR">telecommunications</a>, <a href="/facts/Computer/SQe1aK05">computers</a> (e.g. to distribute precisely timed <a href="/facts/Clock_signal/9UfTzGHx">clock signals</a> in <a href="/facts/Microprocessor/Fx9CaQht">microprocessors</a>), <a href="/facts/Grid-tie_inverter/xhDMPx4e">grid-tie inverters</a> (electronic power converters used to integrate <a href="/facts/Direct_current/r9MNUx84">DC</a> renewable resources and storage elements such as <a href="/facts/Photovoltaics/5Xefaayl">photovoltaics</a> and <a href="/facts/Electric_battery/bqEpm4ue">batteries</a> with the power grid), and other electronic applications. </p>