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Reference.org
Quasi-delay-insensitive circuit
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<p>A quasi-delay-insensitive circuit (QDI circuit) is an <a href="/facts/Asynchronous_circuit/n4ah2j7H">asynchronous</a> <a href="/facts/Circuit_design/wVL89XsX">circuit design</a> methodology employed in <a href="/facts/Digital_logic/RHLulvKI">digital logic design</a>. Developed in response to the performance challenges of building <a href="/facts/Submicroscopic/tICdS8xu">sub-micron</a>, <a href="/facts/Multi-core_processor/ABNb65hQ">multi-core</a> architectures with conventional <a href="/facts/Synchronous_circuit/k3yddBIN">synchronous</a> designs, QDI circuits exhibit lower power consumption, extremely fine-grain <a href="/facts/Pipeline_(computing)/xmHjrPMP">pipelining</a>, high circuit robustness against <a href="/facts/Process_variation_(semiconductor)/1bPJIsvX">process–voltage–temperature variations</a>, on-demand (event-driven) operation, and data-dependent completion time. </p>