Address decoder

In <a href="/facts/Digital_electronics/3kJcKbkw">digital electronics</a>, an address decoder is a <a href="/facts/Binary_decoder/rvbFldxN">binary decoder</a> that has two or more inputs for <a href="/facts/Address_bus/R45TKwS7">address</a> bits and one or more outputs for device selection signals. When the address for a particular device appears on the address inputs, the decoder asserts the selection output for that device. A dedicated, single-output address decoder may be incorporated into each device on an address bus, or a single address decoder may serve multiple devices.
A single address decoder with n address input bits can serve up to 2n devices. Several members of the <a href="/facts/List_of_7400_series_integrated_circuits/WBoUynkg">7400 series</a> of <a href="/facts/Integrated_circuit/fjn6vg7C">integrated circuits</a> can be used as address decoders. For example, when used as an address decoder, the 74154 provides four address inputs and sixteen (i.e., 24) device selector outputs. An address decoder is a particular use of a <a href="/facts/Binary_decoder/rvbFldxN">binary decoder</a> circuit known as a "<a href="/facts/Demultiplexer/lVro0Sfz">demultiplexer</a>" or "demux" (the 74154 is commonly called a "4-to-16 demultiplexer"), which has many other uses besides address decoding.
Address decoders are fundamental building blocks for systems that use <a href="/facts/Bus_(computing)/R45TKwS7">buses</a>. They are represented in all integrated circuit families and processes and in all standard <a href="/facts/FPGA/M8LSGcAU">FPGA</a> and <a href="/facts/Application-specific_integrated_circuit/YGUXpX50">ASIC</a> libraries. They are discussed in introductory textbooks in digital logic design.

Address decoder open-in-new

Address decoder