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Memory ordering
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<p>Memory ordering is the order of accesses to <a href="/facts/Computer_memory/hQKVQ51J">computer memory</a> by a <a href="/facts/CPU/Jxp1bqMV">CPU</a>. Memory ordering depends on both the order of the instructions generated by the <a href="/facts/Compiler/WNfCDFJe">compiler</a> at <a href="/facts/Compile_time/yCdI3oqn">compile time</a> and the execution order of the CPU at <a href="/facts/Execution_(computing)/1fyfGMFm">runtime</a>. However, memory order is of little concern outside of <a href="/facts/Multithreading_(computer_architecture)/ojEKsSNP">multithreading</a> and <a href="/facts/Memory-mapped_I/O/PmLNFq01">memory-mapped I/O</a>, because if the compiler or CPU <a href="/facts/Out-of-order_execution/bM0dQM8m">changes the order of any operations</a>, it must necessarily ensure that the reordering does not change the output of ordinary <a href="/facts/Single-threaded/hh8WHyPd">single-threaded</a> code. </p><p>The memory order is said to be <i>strong</i> or <i>sequentially consistent</i> when either the order of operations cannot change or when such changes have no visible effect on any thread. Conversely, the memory order is called <i>weak</i> or <i>relaxed</i> when one thread cannot predict the order of operations arising from another thread. Many naïvely written <a href="/facts/Parallel_algorithms/nUPzEF4C">parallel algorithms</a> fail when compiled or executed with a weak memory order. The problem is most often solved by inserting <a href="/facts/Memory_barrier/am65f6bs">memory barrier</a> instructions into the program. </p><p>In order to fully utilize the <a href="/facts/Memory_bandwidth/zE5JRtRl">bandwidth</a> of different types of memory such as <a href="/facts/CPU_cache/x8BYFcdv">caches</a> and <a href="/facts/Memory_bank/FWIyfquw">memory banks</a>, few compilers or CPU architectures ensure perfectly strong ordering. Among the commonly used architectures, <a href="/facts/X86-64/cyWvUFlP">x86-64</a> processors have the strongest memory order, but may still defer memory store instructions until after memory load instructions. On the other end of the spectrum, <a href="/facts/DEC_Alpha/4eN7LuXG">DEC Alpha</a> processors make practically no guarantees about memory order. </p>