Latch-up

In <a href="/facts/Electronics/E4JhgISq">electronics</a>, a latch-up is a type of <a href="/facts/Short_circuit/r09vaaeQ">short circuit</a> which can occur in an <a href="/facts/Integrated_circuit/fjn6vg7C">integrated circuit</a> (IC). More specifically, it is the inadvertent creation of a low-<a href="/facts/Electrical_impedance/I06NSXtN">impedance</a> path between the <a href="/facts/Power_supply_rail/3nvssXFG">power supply rails</a> of a <a href="/facts/MOSFET/eTDJT2Km">MOSFET</a> circuit, triggering a <a href="/facts/Parasitic_structure/h7EmtL9D">parasitic structure</a> which disrupts proper functioning of the part, possibly even leading to its destruction due to <a href="/facts/Overcurrent/Sx9FXrUI">overcurrent</a>. A <a href="/facts/Power_cycling/SvRYnEce">power cycle</a> is required to correct this situation.
The parasitic structure is usually equivalent to a <a href="/facts/Thyristor/DYPV2ftl">thyristor</a> (or <a href="/facts/Silicon-controlled_rectifier/ep3HLxmS">SCR</a>), a <a href="/facts/P-n_junction/CaKIdLPg">PNPN</a> structure which acts as a PNP and an NPN <a href="/facts/Bipolar_junction_transistor/9BMcGv5Q">transistor</a> stacked next to each other. During a latch-up when one of the transistors is conducting, the other one begins conducting too. They both keep each other in saturation for as long as the structure is forward-biased and some current flows through it - which usually means until a power-down. The SCR parasitic structure is formed as a part of the totem-pole PMOS and NMOS transistor pair on the output drivers of the gates.
The latch-up does not have to happen between the power rails - it can happen at any place where the required parasitic structure exists. A common cause of latch-up is a positive or negative voltage spike on an input or output pin of a digital chip that exceeds the rail voltage by more than a diode drop. Another cause is the supply voltage exceeding the absolute maximum rating, often from a <a href="/facts/Transient_(oscillation)/mzrDXMvd">transient</a> <a href="/facts/Voltage_spike/XYdAJkje">spike</a> in the power supply. It leads to a <a href="/facts/Avalanche_diode/y7J5DvAq">breakdown</a> of an internal <a href="/facts/P-n_junction/CaKIdLPg">junction</a>. This frequently happens in circuits which use multiple supply voltages that do not come up in the required sequence on power-up, leading to voltages on data lines exceeding the input rating of parts that have not yet reached a nominal supply voltage. Latch-ups can also be caused by an <a href="/facts/Electrostatic_discharge/I55BBYfS">electrostatic discharge</a> event.

Another common cause of latch-ups is <a href="/facts/Ionizing_radiation/vw0d9GaT">ionizing radiation</a> which makes this a significant issue in electronic products designed for space (or very high-altitude) applications. A single-event latch-up is a latch-up caused by a <a href="/facts/Single-event_upset/LoGHTSFw">single-event upset</a>, typically heavy ions or protons from cosmic rays or solar flares.
Single-event latch-up (SEL) can be completely eliminated by several manufacturing techniques, as part of <a href="/facts/Radiation_hardening/nB4Wbctl">radiation hardening</a>.
High-power microwave interference can also trigger latch ups.
Both CMOS integrated circuits and TTL integrated circuits are more susceptible to latch-up at higher temperatures.

Latch-up open-in-new

Latch-up