x86 memory segmentation

x86 memory segmentation is a term for the kind of <a href="/facts/Memory_segmentation/QCUGw5v5">memory segmentation</a> characteristic of the Intel <a href="/facts/X86/Kypq5fgu">x86</a> computer <a href="/facts/Instruction_set_architecture/8p8vwUeE">instruction set architecture</a>. The x86 architecture has supported memory segmentation since the original <a href="/facts/Intel_8086/sS9dlSdK">Intel 8086</a> (1978), but x86 memory segmentation is a plainly descriptive <a href="/facts/Retronym/yBLuNepw">retronym</a>. The introduction of memory segmentation mechanisms in this architecture reflects the legacy of earlier 80xx processors, which initially could only address 16, or later 64 KB of memory (16,384 or 65,536 <a href="/facts/Byte/BNHUp9Qq">bytes</a>), and whose instructions and registers were optimised for the latter. Dealing with larger addresses and more memory was thus comparably slower, as that capability was somewhat grafted-on in the Intel 8086. Memory segmentation could keep programs compatible, relocatable in memory, and by confining significant parts of a program's operation to 64 KB segments, the program could still run faster.
In 1982, the <a href="/facts/Intel_80286/rucEU93g">Intel 80286</a> added support for <a href="/facts/Virtual_memory/Lw2GemF5">virtual memory</a> and <a href="/facts/Memory_protection/3zDwN2SG">memory protection</a>; the original mode was renamed <a href="/facts/Real_mode/wfU8vfjn">real mode</a>, and the new version was named <a href="/facts/Protected_mode/y5u3Gwqq">protected mode</a>. The <a href="/facts/X86-64/cyWvUFlP">x86-64</a> architecture, introduced in 2003, has largely dropped support for segmentation in 64-bit mode.
In both real and protected modes, the system uses 16-bit segment registers to derive the actual memory address. In real mode, the registers CS, DS, SS, and ES point to the currently used program <a href="/facts/Code_segment/tRPrQU7G">code segment</a> (CS), the current <a href="/facts/Data_segment/AR64BUzX">data segment</a> (DS), the current <a href="/facts/Stack_segment/1sMt713v">stack segment</a> (SS), and one extra segment determined by the system programmer (ES). The <a href="/facts/Intel_80386/ag5eSgWv">Intel 80386</a>, introduced in 1985, adds two additional segment registers, FS and GS, with no specific uses defined by the hardware. The way in which the segment registers are used differs between the two modes.
The choice of segment is normally defaulted by the processor according to the function being executed. Instructions are always fetched from the code segment. Any data reference to the stack, including any stack push or pop, uses the stack segment; data references indirected through the BP register typically refer to the stack and so they default to the stack segment. The extra segment is the mandatory destination for string operations (for example MOVS or CMPS); for this one purpose only, the automatically selected segment register cannot be overridden. All other references to data use the data segment by default. The data segment is the default source for string operations, but it can be overridden. FS and GS have no hardware-assigned uses. The instruction format allows an optional segment prefix byte which can be used to override the default segment for selected instructions if desired.

x86 memory segmentation open-in-new

x86 memory segmentation