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Instruction pipelining
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<a href="/facts/Classic_RISC_pipeline/67UhbP04">Basic five-stage pipeline</a><table><tbody><tr><th>Clock cycleInstr. No.</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th></tr><tr><td>1</td><td>IF</td><td>ID</td><td>EX</td><td>MEM</td><td>WB</td><td></td><td></td></tr><tr><td>2</td><td></td><td>IF</td><td>ID</td><td>EX</td><td>MEM</td><td>WB</td><td></td></tr><tr><td>3</td><td></td><td></td><td>IF</td><td>ID</td><td>EX</td><td>MEM</td><td>WB</td></tr><tr><td>4</td><td></td><td></td><td></td><td>IF</td><td>ID</td><td>EX</td><td>MEM</td></tr><tr><td>5</td><td></td><td></td><td></td><td></td><td>IF</td><td>ID</td><td>EX</td></tr><tr><td colspan="8">(IF = Instruction Fetch, ID = Instruction Decode, EX = Execute, MEM = Memory access, WB = Register write back).<p>In the fourth clock cycle (the green column), the earliest instruction is in MEM stage, and the latest instruction has not yet entered the pipeline.</p></td></tr></tbody></table> <p>In <a href="/facts/Computer_engineering/5x1TRKGo">computer engineering</a>, instruction pipelining is a technique for implementing <a href="/facts/Instruction-level_parallelism/2W8qvN8K">instruction-level parallelism</a> within a single processor. Pipelining attempts to keep every part of the processor busy with some instruction by dividing incoming <a href="/facts/Machine_code/bgdQ1Fxf">instructions</a> into a series of sequential steps (the eponymous "<a href="/facts/Pipeline_(computing)/xmHjrPMP">pipeline</a>") performed by different <a href="/facts/Central_processing_unit/Jxp1bqMV">processor units</a> with different parts of instructions processed in parallel. </p>