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POWER8
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<h2 id="design">Design</h2> <p>POWER8 is designed to be a massively multithreaded chip, with each of its cores capable of handling eight hardware threads simultaneously, for a total of 96 threads executed simultaneously on a 12-core chip. The processor makes use of very large amounts of on- and off-chip <a href="/facts/EDRAM/rf8jR3Ds">eDRAM</a> caches, and on-chip memory controllers enable very high bandwidth to memory and system I/O. For most workloads, the chip is said to perform two to three times as fast as its predecessor, the <a href="/facts/POWER7/GKnhcYKC">POWER7</a>.<a class="footnote-ref" id="fnref:4" href="#fn:4"><sup>4</sup></a> </p><p>POWER8 chips comes in 6- or 12-core variants;<a class="footnote-ref" id="fnref:5" href="#fn:5"><sup>5</sup></a><a class="footnote-ref" id="fnref:6" href="#fn:6"><sup>6</sup></a> each version is fabricated in a <a href="/facts/22_nanometer/zr0VI9w6">22 nm</a> <a href="/facts/Silicon_on_insulator/fxSkXYmw">silicon on insulator</a> (SOI) process using 15 metal layers. The 12-core version consists of 4.2 billion transistors<a class="footnote-ref" id="fnref:7" href="#fn:7"><sup>7</sup></a> and is 650 mm2 large while the 6-core version is only 362 mm2 large.<a class="footnote-ref" id="fnref:8" href="#fn:8"><sup>8</sup></a> However the 6- and 12-core variants can have all or just some cores active, so POWER8 processors come with 4, 6, 8, 10 or 12 cores activated. </p> <h3>CAPI</h3> <p class="note">Main article: <a href="/facts/Coherent_Accelerator_Processor_Interface/98AtdIKu">Coherent Accelerator Processor Interface</a></p> <p>Where previous POWER processors use the <a href="/facts/PowerPC_600/NM9PomrW">GX++ bus</a> for external communication, POWER8 removes this from the design and replaces it with the CAPI port (Coherent Accelerator Processor Interface) that is layered on top of <a href="/facts/PCI_Express_3.0/ADhsLCUK">PCI Express 3.0</a>. The CAPI port is used to connect auxiliary specialized processors such as <a href="/facts/Graphics_processing_unit/PTK1RQVp">GPUs</a>, <a href="/facts/Application-specific_integrated_circuit/YGUXpX50">ASICs</a> and <a href="/facts/FPGA/M8LSGcAU">FPGAs</a>.<a class="footnote-ref" id="fnref:9" href="#fn:9"><sup>9</sup></a><a class="footnote-ref" id="fnref:10" href="#fn:10"><sup>10</sup></a> Units attached to the CAPI bus can use the same memory address space as the CPU, thereby reducing the computing path length. At the 2013 <a href="/facts/ACM%2fIEEE_Supercomputing_Conference/vtBfdQHj">ACM/IEEE Supercomputing Conference</a>, IBM and <a href="/facts/Nvidia/8QfCgqbu">Nvidia</a> announced an engineering partnership to closely couple POWER8 with Nvidia GPUs in future <a href="/facts/Supercomputer/HT9NwGAN">HPC</a> systems,<a class="footnote-ref" id="fnref:11" href="#fn:11"><sup>11</sup></a> with the first of them announced as the Power Systems S824L. </p><p>On October 14, 2016, IBM announced the formation of <a href="/facts/Coherent_Accelerator_Processor_Interface/98AtdIKu">OpenCAPI</a>, a new organization to spread adoption of CAPI to other platforms. Initial members are Google, AMD, Xilinx, Micron and Mellanox.<a class="footnote-ref" id="fnref:12" href="#fn:12"><sup>12</sup></a> </p> <h3>OCC</h3> <p>POWER8 also contains a so-called <i>on-chip controller</i> (OCC), which is a power and thermal management microcontroller based on a <a href="/facts/PowerPC_405/X6zS1Rgu">PowerPC 405</a> processor. It has two general-purpose offload engines (GPEs) and 512 <a href="/facts/Kibibyte/BNHUp9Qq">KB</a> of embedded <a href="/facts/Static_random-access_memory/Pmyo4V5e">static RAM</a> (SRAM) (1 KB = 1024 bytes), together with the possibility to access the <a href="/facts/Main_memory/wPHKFpdx">main memory</a> directly, while running an open-source <a href="/facts/Firmware/62UVKIUK">firmware</a>. OCC manages POWER8's operating frequency, voltage, memory bandwidth, and thermal control for both the processor and memory; it can regulate voltages through 1,764 integrated <a href="/facts/Voltage_regulator/RWQATaje">voltage regulators</a> (IVRs) on the fly. Also, the OCC can be programmed to <a href="/facts/Overclocking/wNpjgAFI">overclock</a> the POWER8 processor, or to lower its power consumption by reducing the operating frequency (which is similar to the <a href="/facts/Configurable_TDP/Idcy26tM">configurable TDP</a> found in some of the Intel and AMD processors).<a class="footnote-ref" id="fnref:13" href="#fn:13"><sup>13</sup></a><a class="footnote-ref" id="fnref:14" href="#fn:14"><sup>14</sup></a><a class="footnote-ref" id="fnref:15" href="#fn:15"><sup>15</sup></a><a class="footnote-ref" id="fnref:16" href="#fn:16"><sup>16</sup></a> </p> <h3>Memory Buffer chip</h3> <p>POWER8 splits the memory controller functions by moving some of them away from the processor and closer to the memory. The scheduling logic, the memory energy management, and the <a href="/facts/Reliability%2c_availability_and_serviceability/alWe5yD1">RAS</a> decision point are moved to a so-called Memory Buffer chip (a.k.a. Centaur).<a class="footnote-ref" id="fnref:17" href="#fn:17"><sup>17</sup></a> Offloading certain memory processes to the Memory Buffer chip enables memory access optimizations, saving bandwidth and allowing for faster processor to memory communication.<a class="footnote-ref" id="fnref:18" href="#fn:18"><sup>18</sup></a> It also contains caching structures for an additional 16 <a href="/facts/Mebibyte/BNHUp9Qq">MB</a> of L4 cache per chip (up to 128 MB per processor) (1 MB = 1024 KB). Depending on the system architecture the Memory Buffer chips are placed either on the memory modules (Custom DIMM/CDIMM, for example in S824 and E880 models), or on the memory riser card holding standard DIMMs (for example in S822LC models).<a class="footnote-ref" id="fnref:19" href="#fn:19"><sup>19</sup></a> </p><p>The Memory Buffer chip is connected to the processor using a high-speed multi-lane serial link. The memory channel connecting each buffer chip is capable of writing 2 bytes and reading 1 byte at a time. It runs at 8 <a href="/facts/Gibibyte/BNHUp9Qq">GB</a>/s in the early Entry models,<a class="footnote-ref" id="fnref:20" href="#fn:20"><sup>20</sup></a> later increased in the high-end and the HPC models to 9.6 GB/s with a 40-ns latency,<a class="footnote-ref" id="fnref:21" href="#fn:21"><sup>21</sup></a><a class="footnote-ref" id="fnref:22" href="#fn:22"><sup>22</sup></a><a class="footnote-ref" id="fnref:23" href="#fn:23"><sup>23</sup></a> for a sustained bandwidth of 24 GB/s and 28.8 GB/s per channel respectively. Each processor has two memory controllers with four memory channels each, and the maximum processor to memory buffer bandwidth is 230.4 GB/s per processor. Depending on the model only one controller might be enabled,<a class="footnote-ref" id="fnref:24" href="#fn:24"><sup>24</sup></a> or only two channels per controller could be in use.<a class="footnote-ref" id="fnref:25" href="#fn:25"><sup>25</sup></a> For increased availability the link provides "on-the-fly" lane isolation and repair.<a class="footnote-ref" id="fnref:26" href="#fn:26"><sup>26</sup></a> </p><p>Each Memory Buffer chip has four interfaces allowing to use either <a href="/facts/DDR3/1R1CTNv3">DDR3</a> or <a href="/facts/DDR4/70r37baX">DDR4</a> memory at 1600 MHz with no change to the processor link interface. The resulting 32 memory channels per processor allow peak access rate of 409.6 GB/s between the Memory Buffer chips and the DRAM banks. Initially support was limited to 16 GB, 32 GB and 64 GB DIMMs, allowing up to 1 TB to be addressed by the processor. Later support for 128 GB and 256 GB DIMMs was announced,<a class="footnote-ref" id="fnref:27" href="#fn:27"><sup>27</sup></a><a class="footnote-ref" id="fnref:28" href="#fn:28"><sup>28</sup></a> allowing up to 4 TB per processor. </p> <h2 id="specifications">Specifications</h2> <p>The POWER8<a class="footnote-ref" id="fnref:29" href="#fn:29"><sup>29</sup></a><a class="footnote-ref" id="fnref:30" href="#fn:30"><sup>30</sup></a> core has 64 <a href="/facts/KiB/BNHUp9Qq">KB</a> L1 data cache contained in the load-store unit and 32 KB L1 instruction cache contained in the instruction fetch unit, along with a tightly integrated 512 <a href="/facts/KiB/BNHUp9Qq">KB</a> L2 cache. In a single cycle each core can fetch up to eight instructions, decode and dispatch up to eight instructions, issue and execute up to ten instructions and commit up to eight instructions.<a class="footnote-ref" id="fnref:31" href="#fn:31"><sup>31</sup></a> </p><p>Each POWER8 core consist of primarily the following six <a href="/facts/Execution_unit/uvg54JcX">execution units</a>: </p> <ul><li><a href="/facts/Instruction_fetch_unit/g9A4MCUT">Instruction fetch unit</a> (IFU)</li> <li>Instruction sequencing unit (ISU)</li> <li><a href="/facts/Load%25E2%2580%2593store_unit/8QEBxzRl">Load–store unit</a></li> <li>Fixed-point unit (FXU)</li> <li>Vector and scalar unit (VSU)</li> <li><a href="/facts/Decimal_floating_point/1F9rG2Sn">Decimal</a> <a href="/facts/Floating-point_unit/XWTW2AbF">floating-point unit</a> (DFU)</li></ul> <p>Each core has sixteen execution pipelines: </p> <ul><li>Two fixed-point pipelines</li> <li>Two load-store pipelines</li> <li>Two load pipelines</li> <li>Four <a href="/facts/Double-precision/JYyXXYFM">double-precision</a> <a href="/facts/Floating-point/eIckahxe">floating-point</a> pipelines, which can also act as eight <a href="/facts/Single-precision/e6Fez7BM">single-precision</a> pipelines</li> <li>Two fully symmetric vector pipelines with support for VMX and VSX <a href="/facts/AltiVec/Vn1DY71U">AltiVec</a> instructions.</li> <li>One cryptographic pipeline (<a href="/facts/Advanced_Encryption_Standard/HdXGBY2Q">AES</a>, <a href="/facts/Galois_Counter_Mode/bx43MwfC">Galois Counter Mode</a>, <a href="/facts/SHA-2/P59oPeGq">SHA-2</a>)<a class="footnote-ref" id="fnref:32" href="#fn:32"><sup>32</sup></a></li> <li>One branch execution pipeline</li> <li>One condition register logical pipeline</li> <li>One decimal floating-point pipeline</li></ul> <p>It has a larger issue queue with 4×16 entries, improved branch predictors and can handle twice as many cache misses. Each core is eight-way hardware multithreaded and can be dynamically and automatically partitioned to have either one, two, four or all eight threads active.<a class="footnote-ref" id="fnref:33" href="#fn:33"><sup>33</sup></a> POWER8 also added support for hardware <a href="/facts/Transactional_memory/N7CcDl7w">transactional memory</a>.<a class="footnote-ref" id="fnref:34" href="#fn:34"><sup>34</sup></a><a class="footnote-ref" id="fnref:35" href="#fn:35"><sup>35</sup></a><a class="footnote-ref" id="fnref:36" href="#fn:36"><sup>36</sup></a> IBM estimates that each core is 1.6 times as fast as the POWER7 in single-threaded operations. </p><p>A POWER8 processor is a 6- or 12-chiplet design with variants of either 4, 6, 8, 10 or 12 activated chiplets, in which one chiplet consists of one processing core, 512 KB of <a href="/facts/Static_random-access_memory/Pmyo4V5e">SRAM</a> L2 cache on a 64-byte wide bus (which is twice as wide as on its predecessor<a class="footnote-ref" id="fnref:37" href="#fn:37"><sup>37</sup></a>), and 8 MB of L3 eDRAM cache per chiplet shareable among all chiplets.<a class="footnote-ref" id="fnref:38" href="#fn:38"><sup>38</sup></a> Thus, a six-chiplet processor would have 48 MB of L3 eDRAM cache, while a 12-chiplet processor would have a total of 96 MB of L3 eDRAM cache. The chip can also utilize an up to 128 MB of off-chip eDRAM L4 cache using Centaur companion chips. The on-chip memory controllers can handle 1 TB of RAM and 230 GB/s sustained memory bandwidth. The on-board <a href="/facts/PCI_Express/ADhsLCUK">PCI Express</a> controllers can handle 48 GB/s of I/O to other parts of the system. The cores are designed to operate at clock rates between 2.5 and 5 GHz.<a class="footnote-ref" id="fnref:39" href="#fn:39"><sup>39</sup></a> </p><p>The six-core chips are mounted in pairs on dual-chip modules (DCM) in IBM's <a href="/facts/IBM_Power_Systems/8yTTWKgs">scale out servers</a>. In most configurations not all cores are active, resulting in a variety of configurations where the actual core count differs. The 12-core version is used in the high-end E880 and E880C models. </p><p>IBM's single-chip POWER8 module is called Turismo<a class="footnote-ref" id="fnref:40" href="#fn:40"><sup>40</sup></a> and the dual-chip variant is called Murano.<a class="footnote-ref" id="fnref:41" href="#fn:41"><sup>41</sup></a> PowerCore's modified version is called CP1. </p> <h3>POWER8 with NVLink</h3> <p>This is a revised version of the original 12-core POWER8 from IBM, and used to be called <i>POWER8+</i>. The main new feature is that it has support for Nvidia's bus technology <a href="/facts/NVLink/l5RGqeba">NVLink</a>, connecting up to four NVLink devices directly to the chip. IBM removed the <i>A Bus</i> and PCI interfaces for SMP connections to other POWER8 sockets and replaced them with NVLink interfaces. Connection to a second CPU socket are now provided via the <i>X Bus</i>. Besides that and a slight size increase to 659 mm2, the differences seem minimal compared to previous POWER8 processors.<a class="footnote-ref" id="fnref:42" href="#fn:42"><sup>42</sup></a><a class="footnote-ref" id="fnref:43" href="#fn:43"><sup>43</sup></a><a class="footnote-ref" id="fnref:44" href="#fn:44"><sup>44</sup></a><a class="footnote-ref" id="fnref:45" href="#fn:45"><sup>45</sup></a> </p> <h2 id="licensees">Licensees</h2> <p>On 19 January 2014, the Suzhou PowerCore Technology Company announced that they will join the <a href="/facts/OpenPOWER_Foundation/490VY6za">OpenPOWER Foundation</a> and license the POWER8 core to design custom-made processors for use in <a href="/facts/Big_data/XGtrVg4z">big data</a> and <a href="/facts/Cloud_computing/guhg0FGV">cloud computing</a> applications.<a class="footnote-ref" id="fnref:46" href="#fn:46"><sup>46</sup></a><a class="footnote-ref" id="fnref:47" href="#fn:47"><sup>47</sup></a> </p> <h2 id="variants">Variants</h2> <ul><li>IBM <i> Murano</i> – a 12-core processor with two six-core chips. <a href="/facts/Scalability/jh7JomPa">Scale-out</a> processor is available in configurations with disabled cores.</li> <li>IBM <i>Turismo</i> – a single-chip 12-core processor. <a href="/facts/Scalability/jh7JomPa">Scale-up</a> processor is commercially available for licensing and purchase in configurations with disabled cores.</li> <li>PowerCore <i>CP1</i> – a POWER8 variant with revised security features due to export restrictions between United States and China that will be manufactured in <a href="/facts/GlobalFoundries/lFTS5fbT">GlobalFoundries</a> (formerly IBM's plant) factory in <a href="/facts/East_Fishkill%2c_New_York/HHMyfo3S">East Fishkill, New York</a>. Released in 2015.<a class="footnote-ref" id="fnref:48" href="#fn:48"><sup>48</sup></a><a class="footnote-ref" id="fnref:49" href="#fn:49"><sup>49</sup></a></li></ul> <h2 id="systems">Systems</h2> IBM <a href="/facts/IBM_Power_Systems/8yTTWKgs">Scale Out servers</a>, supporting one or two sockets each carrying a dual-chip module with two six-core POWER8 processors. They come in either <a href="/facts/Rack_unit/Fh9hl0cc">2U or 4U</a> form factors, and one tower configuration. The "L" versions run only <a href="/facts/Linux/9FvCKSTq">Linux</a>, while the others run <a href="/facts/IBM_AIX/cRWERua2">AIX</a>, <a href="/facts/IBM_i/lsIRAUvn">IBM i</a> and Linux. The "LC" versions are built by OpenPOWER partners.<a class="footnote-ref" id="fnref:50" href="#fn:50"><sup>50</sup></a><a class="footnote-ref" id="fnref:51" href="#fn:51"><sup>51</sup></a><a class="footnote-ref" id="fnref:52" href="#fn:52"><sup>52</sup></a> <ul><li><i>Power Systems S812L</i> – 1× POWER8 DCM (4, 6 or 8 cores), 2U</li> <li><i>Power Systems S814</i> – 1× POWER8 DCM (6 or 8 cores), 4U or tower</li> <li><i>Power Systems S822</i> and <i>S822L</i> – 1× or 2× POWER8 DCM (6, 10, 12 or 20 cores), 2U</li> <li><i>Power Systems S824</i> and <i>S824L</i> – 1× or 2× POWER8 DCM (6, 8, 12, 16 or 24 cores), 4U</li> <li><i>Power Systems S821LC "Stratton"</i> – 2× POWER8 <a href="/facts/Single_Chip_Module/lblHmkBX">SCM</a> (8 or 10 cores), 1U. Up to 512 GB DDR4 RAM buffered by four Centaur L4 chips. Manufactured by <a href="/facts/Supermicro/oecEUdg1">Supermicro</a>.<a class="footnote-ref" id="fnref:53" href="#fn:53"><sup>53</sup></a></li> <li><i>Power Systems S822LC for Big Data "Briggs"</i> – 2× POWER8 SCM (8 or 10 cores), 2U. Up to 512 GB DDR4 RAM buffered by four Centaur L4 chips. Manufactured by Supermicro.<a class="footnote-ref" id="fnref:54" href="#fn:54"><sup>54</sup></a></li></ul> <a href="/facts/IBM_Power_Systems/8yTTWKgs">Enterprise servers</a>, supporting nodes with four sockets, each carrying 8-, 10- or 12-core modules, for a maximum of 16 sockets, 128 cores and 16 TB of RAM. These machines can run <a href="/facts/IBM_AIX/cRWERua2">AIX</a>, <a href="/facts/IBM_i/lsIRAUvn">IBM i</a>, or <a href="/facts/Linux/9FvCKSTq">Linux</a>.<a class="footnote-ref" id="fnref:55" href="#fn:55"><sup>55</sup></a> <ul><li><i>Power Systems E850</i> – 2×, 3× or 4× POWER8 DCM (8, 10 or 12 cores), 4U</li> <li><i>Power Systems E870</i> – 1× or 2× 5U nodes, each with four sockets with 8- or 10-core POWER8 single-chip modules, for up to a total of 80 cores</li> <li><i>Power Systems E880</i> – 1x, 2x, 3x or 4x 5U nodes, each with four sockets with 8- or 12-core POWER8 single-chip modules for up to a total of 192 cores</li></ul> <a href="/facts/High_performance_computing/HT9NwGAN">High performance computing</a>: <ul><li><i>Power Systems S812LC</i> – 1× POWER8 SCM (8 or 10 cores), 2U. Manufactured by Tyan.<a class="footnote-ref" id="fnref:56" href="#fn:56"><sup>56</sup></a></li> <li><i>Power Systems S822LC "Firestone"</i> – 2× POWER8 SCM (8 or 10 cores), 2U. Two Nvidia <a href="/facts/Kepler_(microarchitecture)/NU6RAHIQ">Tesla K80</a> <a href="/facts/GPU/PTK1RQVp">GPUs</a> and up to 1 TB commodity DDR3 RAM. Manufactured by <a href="/facts/Wistron/Mz7dke7m">Wistron</a>.<a class="footnote-ref" id="fnref:57" href="#fn:57"><sup>57</sup></a><a class="footnote-ref" id="fnref:58" href="#fn:58"><sup>58</sup></a><a class="footnote-ref" id="fnref:59" href="#fn:59"><sup>59</sup></a><a class="footnote-ref" id="fnref:60" href="#fn:60"><sup>60</sup></a></li> <li><i>Power Systems S822LC for HPC "Minsky"</i> – 2× POWER8+ SCM (8 or 10 cores), 2U. Up to four <a href="/facts/NVLink/l5RGqeba">NVLinked</a> Nvidia <a href="/facts/Pascal_(microarchitecture)/GnmTVMlb">Tesla P100 GPUs</a> and up to 1 TB commodity DDR4 RAM. Manufactured by <a href="/facts/Wistron/Mz7dke7m">Wistron</a>.<a class="footnote-ref" id="fnref:61" href="#fn:61"><sup>61</sup></a><a class="footnote-ref" id="fnref:62" href="#fn:62"><sup>62</sup></a></li></ul> <a href="/facts/Hardware_Management_Console/fH4GzVDA">Hardware Management Console</a> <ul><li><i>7063-CR1 HMC</i> – 1× POWER8 SCM (6 cores), 1U. Based on the SuperMicro "Stratton" design.<a class="footnote-ref" id="fnref:63" href="#fn:63"><sup>63</sup></a></li></ul> Tyan <ul><li>An <a href="/facts/ATX/lzxcKxLF">ATX motherboard</a> with one single-chip POWER8 socket called the SP010GM2NR.<a class="footnote-ref" id="fnref:64" href="#fn:64"><sup>64</sup></a></li> <li><i>Palmetto GN70-BP010</i>, OpenPower reference system. 2U server, with one four-core POWER8 SCM, four RAM sockets, based on a Tyan's motherboard.<a class="footnote-ref" id="fnref:65" href="#fn:65"><sup>65</sup></a><a class="footnote-ref" id="fnref:66" href="#fn:66"><sup>66</sup></a></li> <li><i>Habanero TN-71-BP012</i>. 2U, with one 8 core POWER8 SCM, 32 RAM sockets<a class="footnote-ref" id="fnref:67" href="#fn:67"><sup>67</sup></a><a class="footnote-ref" id="fnref:68" href="#fn:68"><sup>68</sup></a><a class="footnote-ref" id="fnref:69" href="#fn:69"><sup>69</sup></a></li> <li><i>GT75-BP012</i>. 1U, with a single 8- or 10-core POWER8 SCM and 32 sockets for RAM modules<a class="footnote-ref" id="fnref:70" href="#fn:70"><sup>70</sup></a></li></ul> Google <a href="/facts/Google/GT9Sugza">Google</a> has shown a motherboard with two sockets, intended for internal use only.<a class="footnote-ref" id="fnref:71" href="#fn:71"><sup>71</sup></a><a class="footnote-ref" id="fnref:72" href="#fn:72"><sup>72</sup></a> StackVelocity StackVelocity has designed a high-performance reference platform, Saba. Inspur <a href="/facts/Inspur/FKT3kYvc">Inspur</a> has made a deal with IBM to develop server hardware based on POWER8 and related technologies.<a class="footnote-ref" id="fnref:73" href="#fn:73"><sup>73</sup></a><a class="footnote-ref" id="fnref:74" href="#fn:74"><sup>74</sup></a> <ul><li>4U server, two POWER8 sockets.<a class="footnote-ref" id="fnref:75" href="#fn:75"><sup>75</sup></a></li></ul> <a href="/facts/Verari_Technologies/lLk3oJXa">Cirrascale</a> <i>RM4950</i> – 4U, 4-core POWER8 SCM with four Nvidia Tesla K40 accelerators. Based on Tyan's motherboard.<a class="footnote-ref" id="fnref:76" href="#fn:76"><sup>76</sup></a><a class="footnote-ref" id="fnref:77" href="#fn:77"><sup>77</sup></a><a class="footnote-ref" id="fnref:78" href="#fn:78"><sup>78</sup></a><a class="footnote-ref" id="fnref:79" href="#fn:79"><sup>79</sup></a> Zoom Netcom <i>RedPOWER C210</i> and <i>C220</i> – 2U and 4U servers with two POWER8 sockets and 64 sockets for RAM modules.<a class="footnote-ref" id="fnref:80" href="#fn:80"><sup>80</sup></a><a class="footnote-ref" id="fnref:81" href="#fn:81"><sup>81</sup></a> <i>RedPOWER C310</i> and <i>C320</i> – 2U and 4U servers with two CP1 sockets.<a class="footnote-ref" id="fnref:82" href="#fn:82"><sup>82</sup></a> ChuangHe <i>OP-1X</i> – 1U, single socket, 32 RAM slots.<a class="footnote-ref" id="fnref:83" href="#fn:83"><sup>83</sup></a><a class="footnote-ref" id="fnref:84" href="#fn:84"><sup>84</sup></a> <a href="/facts/Rackspace/4S5ehJgY">Rackspace</a> <i>Barreleye</i> – 1U, 2 socket, 32 RAM slots. Based on the <a href="/facts/Open_Compute_Project/nCt85QF1">Open Compute Project</a> platform for use in their OnMetal service.<a class="footnote-ref" id="fnref:85" href="#fn:85"><sup>85</sup></a><a class="footnote-ref" id="fnref:86" href="#fn:86"><sup>86</sup></a><a class="footnote-ref" id="fnref:87" href="#fn:87"><sup>87</sup></a><a class="footnote-ref" id="fnref:88" href="#fn:88"><sup>88</sup></a><a class="footnote-ref" id="fnref:89" href="#fn:89"><sup>89</sup></a> Raptor Computing Systems / Raptor Engineering <i>Talos I</i> – unreleased 4U server or workstation, 1 socket, 8 RAM slots.<a class="footnote-ref" id="fnref:90" href="#fn:90"><sup>90</sup></a> Penguin Computing <i>Magna</i> product series<a class="footnote-ref" id="fnref:91" href="#fn:91"><sup>91</sup></a><a class="footnote-ref" id="fnref:92" href="#fn:92"><sup>92</sup></a> <ul><li><i>Magna 2001</i> (software development)<a class="footnote-ref" id="fnref:93" href="#fn:93"><sup>93</sup></a></li> <li><i>Magna 1015</i> (virtualisation)<a class="footnote-ref" id="fnref:94" href="#fn:94"><sup>94</sup></a><a class="footnote-ref" id="fnref:95" href="#fn:95"><sup>95</sup></a></li> <li><i>Magna 2002</i> and <i>Magna 2002S</i> (machine learning)<a class="footnote-ref" id="fnref:96" href="#fn:96"><sup>96</sup></a><a class="footnote-ref" id="fnref:97" href="#fn:97"><sup>97</sup></a></li></ul> <h2 id="see-also">See also</h2> <ul><li><a href="/facts/IBM_Power_microprocessors/twCjzqAx">IBM Power microprocessors</a></li> <li><a href="/facts/OpenPOWER_Foundation/490VY6za">OpenPOWER Foundation</a></li> <li><a href="/facts/POWER7/GKnhcYKC">POWER7</a></li> <li><a href="/facts/POWER9/1xMKJHsX">POWER9</a></li> <li><a href="/facts/IBM_A2/o4VHVJE8">IBM A2</a></li></ul> <h2 id="external-links">External links</h2> Wikimedia Commons has media related to POWER8 systems. <ul><li><a href="https://www.hotchips.org/wp-content/uploads/hc_archives/hc25/HC25.20-Processors1-epub/HC25.26.210-POWER-Studecheli-IBM.pdf">POWER8 Overview, IBM Power Systems</a> <a href="https://web.archive.org/web/20200806125229/http://www.hotchips.org/wp-content/uploads/hc_archives/hc25/HC25.20-Processors1-epub/HC25.26.210-POWER-Studecheli-IBM.pdf">Archived</a> 2020-08-06 at the <a href="/facts/Wayback_Machine/nmQ3a6JC">Wayback Machine</a> (PDF)</li></ul> <h2 id="references">References</h2> <ol> <li id="fn:1"><p>"You won't find this in your phone: A 4GHz 12-core Power8 for badass boxes". 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