IBM z14

<h2 id="description">Description</h2>
The Processor Unit chip (PU chip) has an area of 696 mm2 (25.3 × 27.5 mm) and consists of 6.1 billion <a href="/facts/Transistor/Bmr8zwL0">transistors</a>.<a class="footnote-ref" id="fnref:6" href="#fn:6">6</a> It is fabricated using GlobalFoundries' <a href="/facts/14_nm/lQYsD92n">14 nm</a> <a href="/facts/FinFET/xox63kP7">FinFET</a> <a href="/facts/Silicon_on_insulator/fxSkXYmw">silicon on insulator</a> <a href="/facts/Semiconductor_device_fabrication/Jd23Mu1z">fabrication process</a>, using 17 layers of metal and supporting speeds of 5.2 <a href="/facts/GHz/6Wshj5qm">GHz</a>, which is higher than its predecessor, the z13.<a class="footnote-ref" id="fnref:7" href="#fn:7">7</a> The PU chip has 10 cores but can have 7–10 cores (or "processor units" in IBM's parlance) enabled depending on configuration. The z14 cores support two-way <a href="/facts/Simultaneous_multithreading/bk8ec9yn">simultaneous multithreading</a> for more applications than previously available.
The PU chip is packaged in a single-chip module, which is the same as its predecessor, but a departure from previous designs which were mounted on large <a href="/facts/Multi-chip_module/AzyVaNNp">multi-chip modules</a>. A computer drawer consists of six PU chips and one Storage Controller (SC) chip containing the L4 cache.<a class="footnote-ref" id="fnref:8" href="#fn:8">8</a>
The cores implement the <a href="/facts/Complex_instruction_set_computer/Ucvyh2xq">CISC</a> <a href="/facts/Z/Architecture/FcKYkGn9">z/Architecture</a> with a <a href="/facts/Superscalar/gPxRAb25">superscalar</a>, <a href="/facts/Out-of-order_execution/bM0dQM8m">out-of-order</a> <a href="/facts/Instruction_pipeline/3zy6CcX1">pipeline</a>. New in z14 is a <a href="/facts/Cryptography/e94PEVau">cryptographic</a> <a href="/facts/Coprocessor/WsVXzAGo">coprocessor</a>, called CPACF, attached to each core, used for <a href="/facts/Random_number_generation/RtXEfbzd">random number generation</a>, <a href="/facts/Hash_function/rk6MlCt3">hashing</a>, <a href="/facts/Encryption/16q29Fdv">encryption</a> and decrypting and compression. Further enhancements include an optimization of the core's pipeline, doubling the on-chip caches, better <a href="/facts/Branch_prediction/pGPhFMj5">branch prediction</a>, a new decimal arithmetic <a href="/facts/SIMD/gQHWQSpo">SIMD</a> engine designed to boost <a href="/facts/COBOL/wVnhqs0k">COBOL</a> and <a href="/facts/PL/I/469mVYgd">PL/I</a> code, a "guarded storage facility" that helps <a href="/facts/Java_(programming_language)/9ScgFyAL">Java</a> applications during <a href="/facts/Garbage_collection_(computer_science)/j2vlIu7g">garbage collection</a>, and other enhancements that increase the cores' performance compared to the predecessors.<a class="footnote-ref" id="fnref:9" href="#fn:9">9</a>
The instruction pipeline has an instruction queue that can fetch 6 instructions per cycle; and issue up to 10 instructions per cycle. Each core has a private 128 <a href="/facts/Kilobyte/jIe6t4yv">KB</a> L1 instruction <a href="/facts/CPU_cache/x8BYFcdv">cache</a>, a private 128 KB L1 data cache, a private 2 <a href="/facts/Megabyte/RBF4XpWb">MB</a> L2 instruction cache, and a private 4 MB L2 data cache. In addition, there is a 128 MB shared L3 cache implemented in <a href="/facts/EDRAM/rf8jR3Ds">eDRAM</a>.<a class="footnote-ref" id="fnref:10" href="#fn:10">10</a>
The z14 chip has on board multi-channel <a href="/facts/DDR4_SDRAM/70r37baX">DDR4 RAM</a> <a href="/facts/Memory_controller/tHq2zlws">memory controller</a> supporting a <a href="/facts/RAID/IpzWWgog">RAID</a>-like configuration to recover from memory faults. The z14 also includes two <a href="/facts/PowerPC_600/NM9PomrW">GX bus</a> as well as two new Gen 3 PCIe controllers for accessing host channel adapters and peripherals.<a class="footnote-ref" id="fnref:11" href="#fn:11">11</a> The PU chips has three X-buses for communications to three neighboring PU chips and the SC chip.

<h2 id="storage-controller">Storage Controller</h2>
A compute drawer consists of two clusters. Each cluster comprises either two or three PU chips. The two clusters share a single Storage Controller chip (SC chip). Even though each PU chip has 128 MB L3 cache shared by the 10 cores and other on-die facilities, the SC chip adds 672 MB off-die <a href="/facts/EDRAM/rf8jR3Ds">eDRAM</a> <a href="/facts/CPU_cache/x8BYFcdv">L4 cache</a> shared by the six PU chips in the drawer. The SC chips also handle the communications between the sets of three PU in the drawer as well as communications between drawers using the A-Bus. The SC chip is manufactured on the same 14 nm process as the z14 PU chips, has 17 metal layers, similarly measures 25.3 × 27.5 mm (696 mm2), but consists of 9.7 billion transistors due to amount of L4 memory and runs at half the clock frequency of the PU chip.<a class="footnote-ref" id="fnref:12" href="#fn:12">12</a>

<h2 id="references">References</h2>

<ol>
<li id="fn:1">"IBM Mainframe Ushers in New Era of Data Protection" (Press release). Archived from the original on 2017-07-19. <a href="https://web.archive.org/web/20170719140917/http://www-03.ibm.com/press/us/en/pressrelease/52805.wss" target="_blank">https://web.archive.org/web/20170719140917/http://www-03.ibm.com/press/us/en/pressrelease/52805.wss</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></li>
<li id="fn:2">"IBM is speeding up encrypted transactions with its super-fast IBM Z mainframe". Archived from the original on August 20, 2017. <a href="https://web.archive.org/web/20170820122133/https://www.theinquirer.net/inquirer/news/3013912/ibm-is-speeding-up-encrypted-transactions-with-its-super-fast-ibm-z-mainframe" target="_blank">https://web.archive.org/web/20170820122133/https://www.theinquirer.net/inquirer/news/3013912/ibm-is-speeding-up-encrypted-transactions-with-its-super-fast-ibm-z-mainframe</a> <a href="#fnref:2" class="footnote-back-ref">↩</a></li>
<li id="fn:3">"IBM Systems Get Breathing Room With Globalfoundries Chip Deal". 20 October 2014. <a href="https://www.enterprisetech.com/2014/10/20/ibm-systems-get-breathing-room-globalfoundries-chip-deal/" target="_blank">https://www.enterprisetech.com/2014/10/20/ibm-systems-get-breathing-room-globalfoundries-chip-deal/</a> <a href="#fnref:3" class="footnote-back-ref">↩</a></li>
<li id="fn:4">"IBM Mainframe Ushers in New Era of Data Protection" (Press release). Archived from the original on 2017-07-19. <a href="https://web.archive.org/web/20170719140917/http://www-03.ibm.com/press/us/en/pressrelease/52805.wss" target="_blank">https://web.archive.org/web/20170719140917/http://www-03.ibm.com/press/us/en/pressrelease/52805.wss</a> <a href="#fnref:4" class="footnote-back-ref">↩</a></li>
<li id="fn:5">"IBM z14 Announced, Support Added To LLVM Clang". <a href="https://www.phoronix.com/scan.php?page=news_item&px=IBM-z14-LLVM-Clang" target="_blank">https://www.phoronix.com/scan.php?page=news_item&px=IBM-z14-LLVM-Clang</a> <a href="#fnref:5" class="footnote-back-ref">↩</a></li>
<li id="fn:6">IBM z14 Technical Guide. 30 September 2016. <a href="https://www.redbooks.ibm.com/abstracts/sg248451.html?Open" target="_blank">https://www.redbooks.ibm.com/abstracts/sg248451.html?Open</a> <a href="#fnref:6" class="footnote-back-ref">↩</a></li>
<li id="fn:7">IBM z14 Technical Guide. 30 September 2016. <a href="https://www.redbooks.ibm.com/abstracts/sg248451.html?Open" target="_blank">https://www.redbooks.ibm.com/abstracts/sg248451.html?Open</a> <a href="#fnref:7" class="footnote-back-ref">↩</a></li>
<li id="fn:8">IBM z14 Technical Guide. 30 September 2016. <a href="https://www.redbooks.ibm.com/abstracts/sg248451.html?Open" target="_blank">https://www.redbooks.ibm.com/abstracts/sg248451.html?Open</a> <a href="#fnref:8" class="footnote-back-ref">↩</a></li>
<li id="fn:9">IBM z14 Technical Guide. 30 September 2016. <a href="https://www.redbooks.ibm.com/abstracts/sg248451.html?Open" target="_blank">https://www.redbooks.ibm.com/abstracts/sg248451.html?Open</a> <a href="#fnref:9" class="footnote-back-ref">↩</a></li>
<li id="fn:10">IBM z14 Technical Guide. 30 September 2016. <a href="https://www.redbooks.ibm.com/abstracts/sg248451.html?Open" target="_blank">https://www.redbooks.ibm.com/abstracts/sg248451.html?Open</a> <a href="#fnref:10" class="footnote-back-ref">↩</a></li>
<li id="fn:11">IBM z14 Technical Guide. 30 September 2016. <a href="https://www.redbooks.ibm.com/abstracts/sg248451.html?Open" target="_blank">https://www.redbooks.ibm.com/abstracts/sg248451.html?Open</a> <a href="#fnref:11" class="footnote-back-ref">↩</a></li>
<li id="fn:12">IBM z14 Technical Guide. 30 September 2016. <a href="https://www.redbooks.ibm.com/abstracts/sg248451.html?Open" target="_blank">https://www.redbooks.ibm.com/abstracts/sg248451.html?Open</a> <a href="#fnref:12" class="footnote-back-ref">↩</a></li>
</ol>

IBM z14 open-in-new

IBM z14