Memory ordering

<h2 id="compile-time-memory-ordering">Compile-time memory ordering</h2>
Most programming languages have some notion of a thread of execution which executes statements in a defined order. Traditional compilers translate high-level expressions to a sequence of low-level instructions relative to a <a href="/facts/Program_counter/BxqulBRq">program counter</a> at the underlying machine level. 
Execution effects are visible at two levels: within the program code at a high level, and at the machine level as viewed by other threads or processing elements in <a href="/facts/Concurrent_programming/yVzQBPr9">concurrent programming</a>, or during debugging when using a hardware debugging aid with access to the machine state (some support for this is often built directly into the CPU or microcontroller as functionally independent circuitry apart from the execution core which continues to operate even when the core itself is halted for static inspection of its execution state). Compile-time memory order concerns itself with the former, and does not concern itself with these other views. 

<h3>General issues of program order</h3>
<h4>Program-order effects of expression evaluation</h4>
During compilation, hardware instructions are often generated at a finer granularity than specified in the high-level code. The primary observable effect in a <a href="/facts/Procedural_programming/7r5xz7kx">procedural programming</a> language is assignment of a new value to a named variable. 

 sum = a + b + c; 
 print(sum);

The print statement follows the statement which assigns to the variable sum, and thus when the print statement references the computed variable sum it references this result as an observable effect of the prior execution sequence. As defined by the rules of program sequence, when the print function call references sum, the value of sum must be that of the most recently executed assignment to the variable sum (in this case the immediately previous statement). 
At the machine level, few machines can add three numbers together in a single instruction, and so the compiler will have to translate this expression into two addition operations. If the semantics of the program language restrict the compiler into translating the expression in left-to-right order (for example), then the generated code will look as if the programmer had written the following statements in the original program: 

 sum = a + b;
 sum = sum + c;

If the compiler is permitted to exploit the <a href="/facts/Associative_property/EQX8lV6r">associative property</a> of addition, it might instead generate: 

 sum = b + c; 
 sum = a + sum;

If the compiler is also permitted to exploit the <a href="/facts/Commutative_property/WaYxJLxd">commutative property</a> of addition, it might instead generate: 

 sum = a + c; 
 sum = sum + b;

Note that the integer data type in most programming languages only follows the algebra for the mathematics integers in the absence of <a href="/facts/Integer_overflow/sVNnSolT">integer overflow</a> and that <a href="/facts/Floating-point_arithmetic/eIckahxe">floating-point arithmetic</a> on the floating point data type available in most programming languages is not commutative in rounding effects, making effects of the order of expression visible in small differences of the computed result (small initial differences may however cascade into arbitrarily large differences over a longer computation). 
If the programmer is concerned about integer overflow or rounding effects in floating point, the same program may be coded at the original high level as follows: 

 sum = a + b; 
 sum = sum + c;

<h4>Program-order effects involving function calls</h4>
Many languages treat the statement boundary as a <a href="/facts/Sequence_point/f4xdSEAx">sequence point</a>, forcing all effects of one statement to be complete before the next statement is executed. This will force the compiler to generate code corresponding to the statement order expressed. Statements are, however, often more complicated, and may contain internal <a href="/facts/Function_call/9vFJrg0A">function calls</a>. 

 sum = f(a) + g(b) + h(c);

At the machine level, calling a function usually involves setting up a <a href="/facts/Stack_frame/1sMt713v">stack frame</a> for the function call, which involves many reads and writes to machine memory. In most compiled languages, the compiler is free to order the function calls f, g, and h as it finds convenient, resulting in large-scale changes of program memory order. In a pure functional programming language, function calls are forbidden from having side effects on the visible program state (other than its <a href="/facts/Return_value/lK7c71aa">return value</a>) and the difference in machine memory order due to function call ordering will be inconsequential to program semantics. In procedural languages, the functions called might have side-effects, such as performing an <a href="/facts/Input/output/WQTE8Jas">I/O operation</a>, or updating a variable in global program scope, both of which produce visible effects with the program model. 
Again, a programmer concerned with these effects can become more pedantic in expressing the original source program: 

 sum = f(a);
 sum = sum + g(b);
 sum = sum + h(c);

In programming languages where the statement boundary is defined as a sequence point, the function calls f, g, and h must now execute in that precise order.

<h3>Specific issues of memory order</h3>
<h4>Program-order effects involving pointer expressions</h4>
Now consider the same summation expressed with pointer indirection, in a language such as C or C++ which supports <a href="/facts/Pointer_(computer_programming)/fPoNzy9b">pointers</a>: 

 sum = *a + *b + *c;

Evaluating the expression *x is termed "<a href="/facts/Dereference_operator/HnG6rwyG">dereferencing</a>" a pointer and involves reading from memory at a location specified by the current value of x. The effects of reading from a pointer are determined by architecture's <a href="/facts/Memory_model_(programming)/RtDrDzjL">memory model</a>. When reading from standard program storage, there are no side-effects due to the order of memory read operations. In <a href="/facts/Embedded_system/a4muX1wU">embedded system</a> programming, it is very common to have <a href="/facts/Memory-mapped_I/O/PmLNFq01">memory-mapped I/O</a> where reads and writes to memory trigger I/O operations, or changes to the processor's operational mode, which are highly visible side effects. For the above example, assume for now that the pointers are pointing to regular program memory, without these side-effects. The compiler is free to reorder these reads in program order as it sees fit, and there will be no program-visible side effects. 
What if assigned value is also pointer indirected? 

 *sum = *a + *b + *c;

Here the language definition is unlikely to allow the compiler to break this apart as follows: 

 // as rewritten by the compiler
 // generally forbidden 
 *sum = *a + *b;
 *sum = *sum + *c;

This would not be viewed as efficient in most instances, and pointer writes have potential side-effects on visible machine state. Since the compiler is not allowed this particular splitting transformation, the only write to the memory location of sum must logically follow the three pointer reads in the value expression. 
Suppose, however, that the programmer is concerned about the visible semantics of integer overflow and breaks the statement apart as the program level as follows: 

 // as directly authored by the programmer 
 // with aliasing concerns 
 *sum = *a + *b; 
 *sum = *sum + *c;

The first statement encodes two memory reads, which must precede (in either order) the first write to *sum. The second statement encodes two memory reads (in either order) which must precede the second update of *sum. This guarantees the order of the two addition operations, but potentially introduces a new problem of address <a href="/facts/Aliasing_(computing)/C7wT3dQy">aliasing</a>: any of these pointers could potentially refer to the same memory location. 
For example, let's assume in this example that *c and *sum are aliased to the same memory location, and rewrite both versions of the program with *sum standing in for both. 

 *sum = *a + *b + *sum;

There are no problems here. The original value of what we originally wrote as *c is lost upon assignment to *sum, and so is the original value of *sum but this was overwritten in the first place and it's of no special concern. 

 // what the program becomes with *c and *sum aliased 
 *sum = *a + *b;
 *sum = *sum + *sum;

Here the original value of *sum is overwritten before its first access, and instead we obtain the algebraic equivalent of: 

 // algebraic equivalent of the aliased case above
 *sum = (*a + *b) + (*a + *b);

which assigns an entirely different value into *sum due to the statement rearrangement. 
Because of possible aliasing effects, pointer expressions are difficult to rearrange without risking visible program effects. In the common case, there might not be any aliasing in effect, so the code appears to run normally as before. But in the edge case where aliasing is present, severe program errors can result. Even if these edge cases are entirely absent in normal execution, it opens the door for a malicious adversary to contrive an input where aliasing exists, potentially leading to a computer security <a href="/facts/Exploit_(computer_security)/EdlqsRJM">exploit</a>. 
A safe reordering of the previous program is as follows: 

 // declare a temporary <a href="/facts/Local_variable/q8sIjyhx">local variable</a> 'temp' of suitable type 
 temp = *a + *b; 
 *sum = temp + *c;

Finally consider the indirect case with added function calls: 

 *sum = f(*a) + g(*b);

The compiler may choose to evaluate *a and *b before either function call, it may defer the evaluation of *b until after the function call f or it may defer the evaluation of *a until after the function call g. If the functions f and g are free from program visible side-effects, all three choices will produce a program with the same visible program effects. If the implementation of f or g contain the side-effect of any pointer write subject to aliasing with pointers a or b, the three choices are liable to produce different visible program effects.

<h4>Memory order in language specification</h4>
In general, compiled languages are not detailed enough in their specification for the compiler to determine formally at compile time which pointers are potentially aliased and which are not. The safest course of action is for the compiler to assume that all pointers are potentially aliased at all times. This level of conservative pessimism tends to produce dreadful performance as compared to the optimistic assumption that no aliasing exists, ever. 
As a result, many high-level compiled languages, such as C/C++, have evolved to have intricate and sophisticated semantic specifications about where the compiler is permitted to make optimistic assumptions in code reordering in pursuit of the highest possible performance, and where the compiler is required to make pessimistic assumptions in code reordering to avoid semantic hazards. 
By far the largest class of side effects in a modern procedural language involve memory write operations, so rules around memory ordering are a dominant component in the definition of program order semantics. The reordering of the functions calls above might appear to be a different consideration, but this usually devolves into concerns about memory effects internal to the called functions interacting with memory operations in the expression which generates the function call. 

<h3>Additional difficulties and complications</h3>
<h4>Optimization under as-if</h4>
Modern compilers sometimes take this a step further by means of an <a href="/facts/As-if_rule/06AsWUGS">as-if rule</a>, in which any reordering is permitted (even across statements) if no effect on the visible program semantics results. Under this rule, the order of operations in the translated code can vary wildly from the specified program order. If the compiler is permitted to make optimistic assumptions about distinct pointer expressions having no alias overlap in a case where such aliasing actually exists (this would normally be classified as an ill-formed program exhibiting <a href="/facts/Undefined_behavior/awUm2vGd">undefined behavior</a>), the adverse results of an aggressive code-optimization transformation are impossible to guess prior to code execution or direct code inspection. The realm of undefined behavior has nearly limitless manifestations. 
It is the responsibility of the programmer to consult the language specification to avoid writing ill-formed programs where the semantics are potentially changed as a result of any legal compiler optimization. <a href="/facts/Fortran/m1KqjcMU">Fortran</a> traditionally places a high burden on the programmer to be aware of these issues, with the <a href="/facts/Systems_programming/urTteIsW">systems programming</a> languages C and C++ not far behind. 
Some high-level languages eliminate pointer constructions altogether, as this level of alertness and attention to detail is considered too high to reliably maintain even among professional programmers. 
A complete grasp of memory order semantics is considered to be an arcane specialization even among the subpopulation of professional systems programmers who are typically best informed in this subject area. Most programmers settle for an adequate working grasp of these issues within the normal domain of their programming expertise. At the extreme end of specialization in memory order semantics are the programmers who author <a href="/facts/Software_framework/EWasA8sG">software frameworks</a> in support of <a href="/facts/Concurrent_computing/yVzQBPr9">concurrent computing</a> models. 

<h4>Aliasing of local variables</h4>
Note that local variables can not be assumed to be free of aliasing if a pointer to such a variable escapes into the wild: 

 sum = f(&a) + g(a);

There is no telling what the function f might have done with the supplied pointer to a, including leaving a copy around in global state which the function g later accesses. In the simplest case, f writes a new value to the variable a, making this expression ill-defined in order of execution. f can be conspicuously prevented from doing this by applying a <a href="/facts/Const_(computer_programming)/Krve5QWn">const qualifier</a> to the declaration of its pointer argument, rendering the expression well defined. Thus the modern culture of C/C++ has become somewhat obsessive about supplying const qualifiers to function argument declarations in all viable cases. 
C and C++ permit the internals of f to <a href="/facts/Type_conversion/FuPD945T">type cast</a> the constness attribute away as a dangerous expedient. If f does this in a way that can break the expression above, it should not be declaring the pointer argument type as const in the first place. 
Other high-level languages tilt toward such a declaration attribute amounting to a strong guarantee with no loop-holes to violate this guarantee provided within the language itself; all bets are off on this language guarantee if your application links a library written in a different programming language (though this is considered to be egregiously bad design). 

<h3>Compile-time memory barrier implementation</h3>
See also: <a href="/facts/Memory_barrier/am65f6bs">Memory barrier</a>
These barriers prevent a compiler from reordering instructions during compile time – they do not prevent reordering by CPU during runtime.

<ul><li>Any of these GNU inline assembler statements forbids the <a href="/facts/GNU_Compiler_Collection/t07jh01k">GCC</a> compiler to reorder read and write commands around it:<a class="footnote-ref" id="fnref:19" href="#fn:19">19</a></li></ul>
asm volatile("" ::: "memory");
__asm__ __volatile__ ("" ::: "memory");

<ul><li>This C11/C++11 function forbids the compiler to reorder read and write commands around it:<a class="footnote-ref" id="fnref:20" href="#fn:20">20</a></li></ul>
atomic_signal_fence(memory_order_acq_rel);

<ul><li><a href="/facts/Intel_C%2B%2B_Compiler/PvwUrzdn">Intel C++ Compiler</a> (ICC/ICL) uses "full compiler fence" intrinsics:<a class="footnote-ref" id="fnref:21" href="#fn:21">21</a><a class="footnote-ref" id="fnref:22" href="#fn:22">22</a></li></ul>
__memory_barrier()

<ul><li><a href="/facts/Microsoft_Visual_C%2B%2B/RM3sbYw5">Microsoft Visual C++</a> compiler (MSVC) supports some intrinsics only for x86/x64 (all of these are deprecated):<a class="footnote-ref" id="fnref:23" href="#fn:23">23</a></li></ul>
_ReadBarrier()
_WriteBarrier()
_ReadWriteBarrier()

<h3>Combined barriers</h3>
In many programming languages different types of barriers can be combined with other operations (like load, store, atomic increment, atomic compare and swap), so no extra memory barrier is needed before or after it (or both). Depending on a CPU architecture being targeted these language constructs will translate to either special instructions, to multiple instructions (i.e. barrier and load), or to normal instruction, depending on hardware memory ordering guarantees.

<h2 id="runtime-memory-ordering">Runtime memory ordering</h2>
<h3>In symmetric multiprocessing (SMP) microprocessor systems</h3>
There are several memory-consistency models for <a href="/facts/Symmetric_multiprocessing/T9CahUsN">SMP</a> systems:

<ul><li>Sequential consistency (all reads and all writes are in-order)</li>
<li>Relaxed consistency (some types of reordering are allowed)
<ul><li>Loads can be reordered after loads (for better working of cache coherency, better scaling)</li>
<li>Loads can be reordered after stores</li>
<li>Stores can be reordered after stores</li>
<li>Stores can be reordered after loads</li></ul></li>
<li>Weak consistency (reads and writes are arbitrarily reordered, limited only by explicit <a href="/facts/Memory_barrier/am65f6bs">memory barriers</a>)</li></ul>
On some CPUs

<ul><li><a href="/facts/Atomic_operation/u3pnNCvs">Atomic operations</a> can be reordered with loads and stores.<a class="footnote-ref" id="fnref:24" href="#fn:24">24</a></li>
<li>There can be incoherent instruction cache pipeline, which prevents <a href="/facts/Self-modifying_code/sbdqYrRp">self-modifying code</a> from being executed without special instruction cache flush/reload instructions.</li>
<li>Dependent loads can be reordered (this is unique for Alpha). If the processor first fetches a pointer to some data and then the data, it might not fetch the data itself but use stale data which it has already cached and not yet invalidated. Allowing this relaxation makes cache hardware simpler and faster but leads to the requirement of memory barriers for readers and writers.<a class="footnote-ref" id="fnref:25" href="#fn:25">25</a> On Alpha hardware (like multiprocessor <a href="/facts/Alpha_21264/lVKS3c4I">Alpha 21264</a> systems) cache line invalidations sent to other processors are processed in lazy fashion by default, unless requested explicitly to be processed between dependent loads. The Alpha architecture specification also allows other forms of dependent loads reordering, for example using speculative data reads ahead of knowing the real pointer to be dereferenced.</li></ul>
Memory ordering in some architectures<a class="footnote-ref" id="fnref:26" href="#fn:26">26</a><a class="footnote-ref" id="fnref:27" href="#fn:27">27</a><table><tbody><tr><th rowspan="2">Type</th><th rowspan="2">Alpha</th><th rowspan="2">ARMv7</th><th rowspan="2">MIPS</th><th colspan="2">RISC-V</th><th rowspan="2">PA-RISC</th><th rowspan="2">POWER</th><th colspan="3">SPARC</th><th rowspan="2">x86 <a class="footnote-ref" id="fnref:28" href="#fn:28">28</a></th><th rowspan="2">AMD64</th><th rowspan="2">IA-64</th><th rowspan="2">z/Architecture</th></tr><tr><th>WMO</th><th>TSO</th><th>RMO</th><th>PSO</th><th>TSO</th></tr><tr><td>Loads can be reordered after loads</td><td>Y</td><td>Y</td><td rowspan="8">depend onimplementation</td><td>Y</td><td></td><td>Y</td><td>Y</td><td>Y</td><td></td><td></td><td></td><td></td><td>Y</td><td></td></tr><tr><td>Loads can be reordered after stores</td><td>Y</td><td>Y</td><td>Y</td><td></td><td>Y</td><td>Y</td><td>Y</td><td></td><td></td><td></td><td></td><td>Y</td><td></td></tr><tr><td>Stores can be reordered after stores</td><td>Y</td><td>Y</td><td>Y</td><td></td><td>Y</td><td>Y</td><td>Y</td><td>Y</td><td></td><td></td><td></td><td>Y</td><td></td></tr><tr><td>Stores can be reordered after loads</td><td>Y</td><td>Y</td><td>Y</td><td>Y</td><td>Y</td><td>Y</td><td>Y</td><td>Y</td><td>Y</td><td>Y</td><td>Y</td><td>Y</td><td>Y</td></tr><tr><td>Atomic can be reordered with loads</td><td>Y</td><td>Y</td><td>Y</td><td></td><td></td><td>Y</td><td>Y</td><td></td><td></td><td></td><td></td><td>Y</td><td></td></tr><tr><td>Atomic can be reordered with stores</td><td>Y</td><td>Y</td><td>Y</td><td></td><td></td><td>Y</td><td>Y</td><td>Y</td><td></td><td></td><td></td><td>Y</td><td></td></tr><tr><td>Dependent loads can be reordered</td><td>Y</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>Incoherent instruction cache/pipeline</td><td>Y</td><td>Y</td><td>Y</td><td>Y</td><td></td><td>Y</td><td>Y</td><td>Y</td><td>Y</td><td>Y</td><td></td><td>Y</td><td></td></tr></tbody></table>

RISC-V memory ordering models

WMO
Weak memory order (default)
TSO
Total store order (only supported with the Ztso extension)
SPARC memory ordering modes

TSO
Total store order (default)
RMO
Relaxed-memory order (not supported on recent CPUs)
PSO
Partial store order (not supported on recent CPUs)
<h3>Hardware memory barrier implementation</h3>
See also: <a href="/facts/Memory_barrier/am65f6bs">Memory barrier</a>
Many architectures with SMP support have special hardware instruction for flushing reads and writes during <a href="/facts/Execution_(computing)/1fyfGMFm">runtime</a>.

<ul><li><a href="/facts/X86/Kypq5fgu">x86</a>, <a href="/facts/X86-64/cyWvUFlP">x86-64</a></li></ul>
lfence (asm), void _mm_lfence(void)
sfence (asm), void _mm_sfence(void)<a class="footnote-ref" id="fnref:29" href="#fn:29">29</a>
mfence (asm), void _mm_mfence(void)<a class="footnote-ref" id="fnref:30" href="#fn:30">30</a>

<ul><li><a href="/facts/PowerPC/DqmM9y50">PowerPC</a></li></ul>
sync (asm)

<ul><li><a href="/facts/Itanium/0wkjSDpe">Itanium</a></li></ul>
mf (asm)

<ul><li><a href="/facts/IBM_POWER_Instruction_Set_Architecture/AptQ0xLu">POWER</a></li></ul>
dcs (asm)

<ul><li><a href="/facts/ARMv7/SALsYA79">ARMv7</a><a class="footnote-ref" id="fnref:33" href="#fn:33">33</a></li></ul>
dmb (asm)
dsb (asm)
isb (asm)

<h4>Compiler support for hardware memory barriers</h4>
Some compilers support <a href="/facts/Intrinsic_function/r0re5n09">builtins</a> that emit hardware memory barrier instructions:

<ul><li><a href="/facts/GNU_Compiler_Collection/t07jh01k">GCC</a>,<a class="footnote-ref" id="fnref:34" href="#fn:34">34</a> version 4.4.0 and later,<a class="footnote-ref" id="fnref:35" href="#fn:35">35</a> has __sync_synchronize.</li>
<li>Since C11 and C++11 an atomic_thread_fence() command was added.</li>
<li>The <a href="/facts/Microsoft_Visual_C%2B%2B/RM3sbYw5">Microsoft Visual C++</a> compiler has MemoryBarrier() macro in the <a href="/facts/Windows_API/RRw4RtTu">Windows API</a> header (deprecated).<a class="footnote-ref" id="fnref:36" href="#fn:36">36</a><a class="footnote-ref" id="fnref:37" href="#fn:37">37</a></li>
<li><a href="/facts/Sun_Studio_Compiler_Suite/Wlj0GcQ4">Sun Studio Compiler Suite</a><a class="footnote-ref" id="fnref:38" href="#fn:38">38</a> has __machine_r_barrier, __machine_w_barrier and __machine_rw_barrier.</li></ul>
<h2 id="see-also">See also</h2>
<ul><li><a href="/facts/Memory_model_(programming)/RtDrDzjL">Memory model (programming)</a></li></ul>

<h2 id="further-reading">Further reading</h2>
<ul><li><a href="http://www.ai.mit.edu/projects/aries/papers/consistency/computer_29_12_dec1996_p66.pdf">Shared Memory Consistency Models: A Tutorial</a> by Sarita V Adve and Kourosh Gharachorloo</li>
<li><a href="http://www.rdrop.com/users/paulmck/scalability/paper/ordering.2007.09.19a.pdf">Memory Ordering in Modern Microprocessors</a> by Paul E McKenney</li>
<li><a href="https://preshing.com/20120930/weak-vs-strong-memory-models/">Weak vs. Strong Memory Models</a> by Jeff Preshing</li>
<li><a href="https://lwn.net/Articles/718628/">A formal kernel memory-ordering model</a> by Jade Alglave et al.</li>
<li><a href="https://www.youtube.com/watch?v=WUfvvFD5tAA">IA (Intel Architecture) Memory Ordering</a> on <a href="/facts/YouTube_video_(identifier)/db276jst">YouTube</a> - Google Tech Talk by Richard L Hudson</li>
<li>Computer Architecture — A quantitative approach. 4th edition. J Hennessy, D Patterson, 2007. Chapter 4.6</li></ul>

<h2 id="references">References</h2>

<ol>
<li id="fn:1">Preshing, Jeff (30 September 2012). "Weak vs. Strong Memory Models". Preshing on Programming. Retrieved 3 August 2024. <a href="https://preshing.com/20120930/weak-vs-strong-memory-models/" target="_blank">https://preshing.com/20120930/weak-vs-strong-memory-models/</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></li>
<li id="fn:2">Howells, David; McKenney, Paul E; Deacon, Will; Zijlstra, Peter. "Linux Kernel Memory Barriers". The Linux Kernel Archives. Retrieved 3 August 2024. <a href="https://www.kernel.org/doc/Documentation/memory-barriers.txt" target="_blank">https://www.kernel.org/doc/Documentation/memory-barriers.txt</a> <a href="#fnref:2" class="footnote-back-ref">↩</a></li>
<li id="fn:3">Preshing, Jeff (30 September 2012). "Weak vs. Strong Memory Models". Preshing on Programming. Retrieved 3 August 2024. <a href="https://preshing.com/20120930/weak-vs-strong-memory-models/" target="_blank">https://preshing.com/20120930/weak-vs-strong-memory-models/</a> <a href="#fnref:3" class="footnote-back-ref">↩</a></li>
<li id="fn:4">Howells, David; McKenney, Paul E; Deacon, Will; Zijlstra, Peter. "Linux Kernel Memory Barriers". The Linux Kernel Archives. Retrieved 3 August 2024. <a href="https://www.kernel.org/doc/Documentation/memory-barriers.txt" target="_blank">https://www.kernel.org/doc/Documentation/memory-barriers.txt</a> <a href="#fnref:4" class="footnote-back-ref">↩</a></li>
<li id="fn:5">Preshing, Jeff (25 June 2012). "Memory Ordering at Compile Time". Preshing on Programming. Retrieved 3 August 2024. <a href="https://preshing.com/20120625/memory-ordering-at-compile-time/" target="_blank">https://preshing.com/20120625/memory-ordering-at-compile-time/</a> <a href="#fnref:5" class="footnote-back-ref">↩</a></li>
<li id="fn:6">Preshing, Jeff (30 September 2012). "Weak vs. Strong Memory Models". Preshing on Programming. Retrieved 3 August 2024. <a href="https://preshing.com/20120930/weak-vs-strong-memory-models/" target="_blank">https://preshing.com/20120930/weak-vs-strong-memory-models/</a> <a href="#fnref:6" class="footnote-back-ref">↩</a></li>
<li id="fn:7">Sewell, Peter. "Relaxed-Memory Concurrency". University of Cambridge. Retrieved 3 August 2024. <a href="https://www.cl.cam.ac.uk/~pes20/weakmemory/" target="_blank">https://www.cl.cam.ac.uk/~pes20/weakmemory/</a> <a href="#fnref:7" class="footnote-back-ref">↩</a></li>
<li id="fn:8">Preshing, Jeff (30 September 2012). "Weak vs. Strong Memory Models". Preshing on Programming. Retrieved 3 August 2024. <a href="https://preshing.com/20120930/weak-vs-strong-memory-models/" target="_blank">https://preshing.com/20120930/weak-vs-strong-memory-models/</a> <a href="#fnref:8" class="footnote-back-ref">↩</a></li>
<li id="fn:9">Sewell, Peter. "Relaxed-Memory Concurrency". University of Cambridge. Retrieved 3 August 2024. <a href="https://www.cl.cam.ac.uk/~pes20/weakmemory/" target="_blank">https://www.cl.cam.ac.uk/~pes20/weakmemory/</a> <a href="#fnref:9" class="footnote-back-ref">↩</a></li>
<li id="fn:10">McKenney, Paul E (19 September 2007). "Memory Ordering in Modern Microprocessors" (PDF). Retrieved 3 August 2024. <a href="http://www.rdrop.com/users/paulmck/scalability/paper/ordering.2007.09.19a.pdf" target="_blank">http://www.rdrop.com/users/paulmck/scalability/paper/ordering.2007.09.19a.pdf</a> <a href="#fnref:10" class="footnote-back-ref">↩</a></li>
<li id="fn:11">Torvalds, Linus (8 December 2003). "Re: branch prediction, renaming, joins". Retrieved 3 August 2024. <a href="/wiki/Linus_Torvalds" target="_blank">/wiki/Linus_Torvalds</a> <a href="#fnref:11" class="footnote-back-ref">↩</a></li>
<li id="fn:12">Torvalds, Linus (8 December 2003). "Re: branch prediction, renaming, joins". Retrieved 3 August 2024. <a href="/wiki/Linus_Torvalds" target="_blank">/wiki/Linus_Torvalds</a> <a href="#fnref:12" class="footnote-back-ref">↩</a></li>
<li id="fn:13">Manson, Jeremy; Goetz, Brian (February 2004). "JSR 133 (Java Memory Model) FAQ". University of Maryland. Retrieved 3 August 2024. <a href="http://www.cs.umd.edu/~pugh/java/memoryModel/jsr-133-faq.html" target="_blank">http://www.cs.umd.edu/~pugh/java/memoryModel/jsr-133-faq.html</a> <a href="#fnref:13" class="footnote-back-ref">↩</a></li>
<li id="fn:14">Preshing, Jeff (30 September 2012). "Weak vs. Strong Memory Models". Preshing on Programming. Retrieved 3 August 2024. <a href="https://preshing.com/20120930/weak-vs-strong-memory-models/" target="_blank">https://preshing.com/20120930/weak-vs-strong-memory-models/</a> <a href="#fnref:14" class="footnote-back-ref">↩</a></li>
<li id="fn:15">McKenney, Paul E (19 September 2007). "Memory Ordering in Modern Microprocessors" (PDF). Retrieved 3 August 2024. <a href="http://www.rdrop.com/users/paulmck/scalability/paper/ordering.2007.09.19a.pdf" target="_blank">http://www.rdrop.com/users/paulmck/scalability/paper/ordering.2007.09.19a.pdf</a> <a href="#fnref:15" class="footnote-back-ref">↩</a></li>
<li id="fn:16">McKenney, Paul E (19 September 2007). "Memory Ordering in Modern Microprocessors" (PDF). Retrieved 3 August 2024. <a href="http://www.rdrop.com/users/paulmck/scalability/paper/ordering.2007.09.19a.pdf" target="_blank">http://www.rdrop.com/users/paulmck/scalability/paper/ordering.2007.09.19a.pdf</a> <a href="#fnref:16" class="footnote-back-ref">↩</a></li>
<li id="fn:17">"Intel 64 Architecture Memory Ordering White Paper" (PDF). Intel. August 2007. Retrieved 3 August 2024. <a href="https://www.cs.cmu.edu/~410-f10/doc/Intel_Reordering_318147.pdf" target="_blank">https://www.cs.cmu.edu/~410-f10/doc/Intel_Reordering_318147.pdf</a> <a href="#fnref:17" class="footnote-back-ref">↩</a></li>
<li id="fn:18">McKenney, Paul E (19 September 2007). "Memory Ordering in Modern Microprocessors" (PDF). Retrieved 3 August 2024. <a href="http://www.rdrop.com/users/paulmck/scalability/paper/ordering.2007.09.19a.pdf" target="_blank">http://www.rdrop.com/users/paulmck/scalability/paper/ordering.2007.09.19a.pdf</a> <a href="#fnref:18" class="footnote-back-ref">↩</a></li>
<li id="fn:19">GCC compiler-gcc.h Archived 2011-07-24 at the Wayback Machine <a href="http://lxr.linux.no/linux+v2.6.31/include/linux/compiler-gcc.h#L12" target="_blank">http://lxr.linux.no/linux+v2.6.31/include/linux/compiler-gcc.h#L12</a> <a href="#fnref:19" class="footnote-back-ref">↩</a></li>
<li id="fn:20">"std::atomic_signal_fence". ccpreference. <a href="http://en.cppreference.com/w/cpp/atomic/atomic_signal_fence" target="_blank">http://en.cppreference.com/w/cpp/atomic/atomic_signal_fence</a> <a href="#fnref:20" class="footnote-back-ref">↩</a></li>
<li id="fn:21">ECC compiler-intel.h Archived 2011-07-24 at the Wayback Machine <a href="http://lxr.linux.no/linux+v2.6.31/include/linux/compiler-intel.h#L16" target="_blank">http://lxr.linux.no/linux+v2.6.31/include/linux/compiler-intel.h#L16</a> <a href="#fnref:21" class="footnote-back-ref">↩</a></li>
<li id="fn:22">Intel(R) C++ Compiler Intrinsics ReferenceCreates a barrier across which the compiler will not schedule any data access instruction. The compiler may allocate local data in registers across a memory barrier, but not global data. <a href="https://web.archive.org/web/20090904073120/http://software.intel.com/file/6373" target="_blank">https://web.archive.org/web/20090904073120/http://software.intel.com/file/6373</a> <a href="#fnref:22" class="footnote-back-ref">↩</a></li>
<li id="fn:23">"_ReadWriteBarrier". Microsoft Learn. 3 August 2021. <a href="https://learn.microsoft.com/en-us/cpp/intrinsics/readwritebarrier" target="_blank">https://learn.microsoft.com/en-us/cpp/intrinsics/readwritebarrier</a> <a href="#fnref:23" class="footnote-back-ref">↩</a></li>
<li id="fn:24">Victor Alessandrini, 2015. Shared Memory Application Programming: Concepts and Strategies in Multicore Application Programming. Elsevier Science. p. 176. ISBN 978-0-12-803820-8. <a href="/wiki/ISBN_(identifier)" target="_blank">/wiki/ISBN_(identifier)</a> <a href="#fnref:24" class="footnote-back-ref">↩</a></li>
<li id="fn:25">Reordering on an Alpha processor by Kourosh Gharachorloo <a href="http://www.cs.umd.edu/~pugh/java/memoryModel/AlphaReordering.html" target="_blank">http://www.cs.umd.edu/~pugh/java/memoryModel/AlphaReordering.html</a> <a href="#fnref:25" class="footnote-back-ref">↩</a></li>
<li id="fn:26">McKenney, Paul E (19 September 2007). "Memory Ordering in Modern Microprocessors" (PDF). Retrieved 3 August 2024. <a href="http://www.rdrop.com/users/paulmck/scalability/paper/ordering.2007.09.19a.pdf" target="_blank">http://www.rdrop.com/users/paulmck/scalability/paper/ordering.2007.09.19a.pdf</a> <a href="#fnref:26" class="footnote-back-ref">↩</a></li>
<li id="fn:27">McKenney, Paul E (7 June 2010). "Memory Barriers: a Hardware View for Software Hackers" (PDF). p. 16. Retrieved 3 August 2024. Figure 5. <a href="http://www.rdrop.com/users/paulmck/scalability/paper/whymb.2010.06.07c.pdf#page=16" target="_blank">http://www.rdrop.com/users/paulmck/scalability/paper/whymb.2010.06.07c.pdf#page=16</a> <a href="#fnref:27" class="footnote-back-ref">↩</a></li>
<li id="fn:28">This column indicates the behaviour of the vast majority of x86 processors. Some rare specialised x86 processors (IDT WinChip manufactured around 1998) may have weaker 'oostore' memory ordering.[17] <a href="#fnref:28" class="footnote-back-ref">↩</a></li>
<li id="fn:29">SFENCE — Store Fence <a href="http://www.softeng.rl.ac.uk/st/archive/SoftEng/SESP/html/SoftwareTools/vtune/users_guide/mergedProjects/analyzer_ec/mergedProjects/reference_olh/mergedProjects/instructions/instruct32_hh/vc287.htm" target="_blank">http://www.softeng.rl.ac.uk/st/archive/SoftEng/SESP/html/SoftwareTools/vtune/users_guide/mergedProjects/analyzer_ec/mergedProjects/reference_olh/mergedProjects/instructions/instruct32_hh/vc287.htm</a> <a href="#fnref:29" class="footnote-back-ref">↩</a></li>
<li id="fn:30">MFENCE — Memory Fence <a href="http://www.softeng.rl.ac.uk/st/archive/SoftEng/SESP/html/SoftwareTools/vtune/users_guide/mergedProjects/analyzer_ec/mergedProjects/reference_olh/mergedProjects/instructions/instruct32_hh/vc172.htm" target="_blank">http://www.softeng.rl.ac.uk/st/archive/SoftEng/SESP/html/SoftwareTools/vtune/users_guide/mergedProjects/analyzer_ec/mergedProjects/reference_olh/mergedProjects/instructions/instruct32_hh/vc172.htm</a> <a href="#fnref:30" class="footnote-back-ref">↩</a></li>
<li id="fn:31">"MIPS® Coherence Protocol Specification, Revision 01.01" (PDF). p. 26. Retrieved 2023-12-15. <a href="https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00605-2B-CMPCOHERE-AFP-01.01.pdf" target="_blank">https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00605-2B-CMPCOHERE-AFP-01.01.pdf</a> <a href="#fnref:31" class="footnote-back-ref">↩</a></li>
<li id="fn:32">"MIPS instruction set R5" (PDF). p. 59-60. Retrieved 2023-12-15. <a href="https://training.mips.com/basic_mips/PDF/Instruction_Set.pdf" target="_blank">https://training.mips.com/basic_mips/PDF/Instruction_Set.pdf</a> <a href="#fnref:32" class="footnote-back-ref">↩</a></li>
<li id="fn:33">Data Memory Barrier, Data Synchronization Barrier, and Instruction Synchronization Barrier. <a href="http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0489c/CIHGHHIE.html" target="_blank">http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0489c/CIHGHHIE.html</a> <a href="#fnref:33" class="footnote-back-ref">↩</a></li>
<li id="fn:34">Atomic Builtins <a href="https://gcc.gnu.org/onlinedocs/gcc-4.1.2/gcc/Atomic-Builtins.html" target="_blank">https://gcc.gnu.org/onlinedocs/gcc-4.1.2/gcc/Atomic-Builtins.html</a> <a href="#fnref:34" class="footnote-back-ref">↩</a></li>
<li id="fn:35">"36793 – x86-64 does not get __sync_synchronize right". <a href="https://gcc.gnu.org/bugzilla/show_bug.cgi?id=36793" target="_blank">https://gcc.gnu.org/bugzilla/show_bug.cgi?id=36793</a> <a href="#fnref:35" class="footnote-back-ref">↩</a></li>
<li id="fn:36">"MemoryBarrier function (winnt.h) - Win32 apps". Microsoft Learn. 6 October 2021. <a href="https://learn.microsoft.com/en-us/windows/win32/api/winnt/nf-winnt-memorybarrier" target="_blank">https://learn.microsoft.com/en-us/windows/win32/api/winnt/nf-winnt-memorybarrier</a> <a href="#fnref:36" class="footnote-back-ref">↩</a></li>
<li id="fn:37">"_ReadWriteBarrier". Microsoft Learn. 3 August 2021. <a href="https://learn.microsoft.com/en-us/cpp/intrinsics/readwritebarrier" target="_blank">https://learn.microsoft.com/en-us/cpp/intrinsics/readwritebarrier</a> <a href="#fnref:37" class="footnote-back-ref">↩</a></li>
<li id="fn:38">Handling Memory Ordering in Multithreaded Applications with Oracle Solaris Studio 12 Update 2: Part 2, Memory Barriers and Memory Fence [1] <a href="http://www.oracle.com/technetwork/server-storage/solarisstudio/documentation/oss-memory-barriers-fences-176056.pdf" target="_blank">http://www.oracle.com/technetwork/server-storage/solarisstudio/documentation/oss-memory-barriers-fences-176056.pdf</a> <a href="#fnref:38" class="footnote-back-ref">↩</a></li>
</ol>

Memory ordering open-in-new

Memory ordering