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Depletion and enhancement modes
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<h2 id="alternative-terminology">Alternative terminology</h2> <p>Some sources say "depletion type" and "enhancement type" for the device types as described in this article as "depletion mode" and "enhancement mode", and apply the "mode" terms for which direction the gate–source voltage differs from zero.<a class="footnote-ref" id="fnref:1" href="#fn:1"><sup>1</sup></a> Moving the gate voltage toward the drain voltage "enhances" the conduction in the channel, so this defines the enhancement mode of operation, while moving the gate away from the drain depletes the channel, so this defines depletion mode. </p> <h2 id="enhancement-load-and-depletion-load-logic-families">Enhancement-load and depletion-load logic families</h2> <p><a href="/facts/Depletion-load_NMOS_logic/9xAIaQtl">Depletion-load NMOS logic</a> refers to the logic family that became dominant in silicon <a href="/facts/VLSI/l1Wgqr27">VLSI</a> in the latter half of the 1970s; the process supported both enhancement-mode and depletion-mode transistors, and typical logic circuits used enhancement-mode devices as pull-down switches and depletion-mode devices as loads, or pull-ups. Logic families built in older processes that did not support depletion-mode transistors were retrospectively referred to as <i>enhancement-load</i> logic, or as <i>saturated-load</i> logic, since the enhancement-mode transistors were typically connected with gate to the VDD supply and operated in the saturation region (sometimes the gates are biased to a higher VGG voltage and operated in the linear region, for a better <a href="/facts/Power%25E2%2580%2593delay_product/nb3Xv3FS">power–delay product</a> (PDP), but the loads then take more area).<a class="footnote-ref" id="fnref:2" href="#fn:2"><sup>2</sup></a> Alternatively, rather than static logic gates, <a href="/facts/Dynamic_logic_(digital_logic)/jgQtLWyn">dynamic logic</a> such as <a href="/facts/Four-phase_logic/rkjhMVXz">four-phase logic</a> was sometimes used in processes that did not have depletion-mode transistors available. </p><p>For example, the 1971 <a href="/facts/Intel_4004/kAoetjSU">Intel 4004</a> used enhancement-load silicon-gate <a href="/facts/PMOS_logic/DWmuIrcn">PMOS logic</a>, and the 1976 <a href="/facts/Zilog_Z80/Jeqe2h55">Zilog Z80</a> used depletion-load silicon-gate NMOS. </p> <h2 id="history">History</h2> <p>The original two types of MOSFET logic gates, PMOS and NMOS, were developed by Frosch and Derick in 1957 at Bell Labs.<a class="footnote-ref" id="fnref:3" href="#fn:3"><sup>3</sup></a> In 1963, both depletion- and enhancement-mode MOSFETs were described by Steve R. Hofstein and Fred P. Heiman at <a href="/facts/RCA_Laboratories/J4CvrdeS">RCA Laboratories</a>.<a class="footnote-ref" id="fnref:4" href="#fn:4"><sup>4</sup></a> In 1966, T. P. Brody and H. E. Kunig at <a href="/facts/Westinghouse_Electric/Nln2BzI3">Westinghouse Electric</a> fabricated enhancement- and depletion-mode <a href="/facts/Indium_arsenide/GMhtPVbU">indium arsenide</a> (InAs) MOS <a href="/facts/Thin-film_transistors/rhe3Y936">thin-film transistors</a> (TFTs).<a class="footnote-ref" id="fnref:5" href="#fn:5"><sup>5</sup></a><a class="footnote-ref" id="fnref:6" href="#fn:6"><sup>6</sup></a> In 2022, the first dual-mode organic transistor that behaves in both depletion mode and enhancement mode was reported by a team at University of California-Santa Barbara.<a class="footnote-ref" id="fnref:7" href="#fn:7"><sup>7</sup></a> </p> <h2 id="references">References</h2> <ol> <li id="fn:1"><p>John J. Adams (2001). Mastering Electronics Workbench. McGraw-Hill Professional. p. 192. ISBN 978-0-07-134483-8. <a href="978-0-07-134483-8" target="_blank">978-0-07-134483-8</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></p></li> <li id="fn:2"><p>Jerry C. Whitaker (2005). Microelectronics (2nd ed.). CRC Press. p. 6-7–6-10. ISBN 978-0-8493-3391-0. <a href="978-0-8493-3391-0" target="_blank">978-0-8493-3391-0</a> <a href="#fnref:2" class="footnote-back-ref">↩</a></p></li> <li id="fn:3"><p>Frosch, C. J.; Derick, L (1957). "Surface Protection and Selective Masking during Diffusion in Silicon". Journal of the Electrochemical Society. 104 (9): 547. doi:10.1149/1.2428650. <a href="https://iopscience.iop.org/article/10.1149/1.2428650" target="_blank">https://iopscience.iop.org/article/10.1149/1.2428650</a> <a href="#fnref:3" class="footnote-back-ref">↩</a></p></li> <li id="fn:4"><p>Hofstein, Steve R.; Heiman, Fred P. (September 1963). "The silicon insulated-gate field-effect transistor". Proceedings of the IEEE. 51 (9): 1190–1202. doi:10.1109/PROC.1963.2488. <a href="/wiki/Doi_(identifier)" target="_blank">/wiki/Doi_(identifier)</a> <a href="#fnref:4" class="footnote-back-ref">↩</a></p></li> <li id="fn:5"><p>Woodall, Jerry M. (2010). Fundamentals of III-V Semiconductor MOSFETs. Springer Science & Business Media. pp. 2–3. ISBN 9781441915474. <a href="9781441915474" target="_blank">9781441915474</a> <a href="#fnref:5" class="footnote-back-ref">↩</a></p></li> <li id="fn:6"><p>Brody, T. P.; Kunig, H. E. (October 1966). "A HIGH-GAIN InAs THIN-FILM TRANSISTOR". Applied Physics Letters. 9 (7): 259–260. Bibcode:1966ApPhL...9..259B. doi:10.1063/1.1754740. ISSN 0003-6951. <a href="https://doi.org/10.1063%2F1.1754740" target="_blank">https://doi.org/10.1063%2F1.1754740</a> <a href="#fnref:6" class="footnote-back-ref">↩</a></p></li> <li id="fn:7"><p>Nguyen-Dang, Tung; Visell, Yon; Nguyen, Thuc-Quyen; {et al} (May 2022). "Dual-mode orgnic electrochemical transistors based on self-doped conjugated polyelectrolytes for reconfigure electronics". Advanced Materials. doi:10.1002/adma.202200274. <a href="/wiki/Doi_(identifier)" target="_blank">/wiki/Doi_(identifier)</a> <a href="#fnref:7" class="footnote-back-ref">↩</a></p></li> </ol>